請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91446完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 廖洺漢 | zh_TW |
| dc.contributor.advisor | Ming-Han Liao | en |
| dc.contributor.author | 詹益誠 | zh_TW |
| dc.contributor.author | Yi-Cheng Chan | en |
| dc.date.accessioned | 2024-01-26T16:32:39Z | - |
| dc.date.available | 2024-01-27 | - |
| dc.date.copyright | 2024-01-26 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2024-01-07 | - |
| dc.identifier.citation | [1] R. R. Schaller, “Moore''s law: past, present and future,” IEEE spectrum, vol. 34, no. 6, pp. 52-59, 1997.
[2] J. Stoner. "What Is Moore’s Law and How Does It Impact AI ?," https://www.unite.ai/moores-law/. [3] D. Sekar, C. King, B. Dang, T. Spencer, H. Thacker, P. Joseph, M. Bakir, and J. Meindl, “A 3D-IC technology with integrated microchannel cooling,” in Proc. 2008 International Interconnect Technology Conference, 2008, pp. 13-15. [4] "Technology. Innovation. Sustainability.," Jun., 2023; https://www.cadence.com/en_US/home.html. [5] K. Gibb. Jun., 2023; https://www.eettaiwan.com/20160510nt31-packaging-technology/. [6] S. Li, S. Raju, C. Zhou, and M. Chan, “Carbon nanotube contact plug on silicide for CMOS compatible interconnect,” IEEE Electron Device Letters, vol. 37, no. 6, pp. 793-796, 2016. [7] E. Goldmann, M. Górski, and B. Klemczak, “Recent advancements in carbon nano-infused cementitious composites,” Materials, vol. 14, no. 18, pp. 5176, 2021. [8] J. Lau, P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, K. Saito, Y. Hsin, P. Chang, and Y. Chang, “Redistribution layers (RDLs) for 2.5 D/3D IC integration,” Journal of Microelectronics and Electronic Packaging, vol. 11, no. 1, pp. 16-24, 2014. [9] "Intel Foveros Technology Explained," Jun., 2023; https://www.intel.com/content/www/us/en/homepage.html. [10] "Samsung Announces Availability of its Silicon-Proven 3D IC Technology for High-Performance Applications," Jun., 2023; https://news.samsung.com/global/samsung-announces-availability-of-its-silicon-proven-3d-ic-technology-for-high-performance-applications. [11] "The Chronicle of CoWoS," Jun., 2023; https://3dfabric.tsmc.com/chinese/dedicatedFoundry/technology/cowos.htm. [12] M. Motoyoshi, “Through-silicon via (TSV),” Proceedings of the IEEE, vol. 97, no. 1, pp. 43-48, 2009. [13] M. Resano, E. Bolea-Fernández, E. Mozas, M. R. Flórez, P. Grinberg, and R. E. Sturgeon, “Simultaneous determination of Co, Fe, Ni and Pb in carbon nanotubes by means of solid sampling high-resolution continuum source graphite furnace atomic absorption spectrometry,” Journal of Analytical Atomic Spectrometry, vol. 28, no. 5, pp. 657-665, 2013. [14] C. Emmenegger, J.-M. Bonard, P. Mauron, P. Sudan, A. Lepora, B. Grobety, A. Züttel, and L. Schlapbach, “Synthesis of carbon nanotubes over Fe catalyst on aluminium and suggested growth mechanism,” Carbon, vol. 41, no. 3, pp. 539-547, 2003. [15] Z. Shi, Y. Lian, F. H. Liao, X. Zhou, Z. Gu, Y. Zhang, S. Iijima, H. Li, K. T. Yue, and S.-L. Zhang, “Large scale synthesis of single-wall carbon nanotubes by arc-discharge method,” Journal of physics and chemistry of solids, vol. 61, no. 7, pp. 1031-1036, 2000. [16] H.-Y. Lin, N. Basu, S.-C. Chen, M.-H. Lee, and M.-H. Liao, “The demonstration of low-temperature (350° C) grown carbon nano-tubes for the applications of through silicon via in 3D stacking and power-via,” Applied Physics Letters, vol. 121, no. 23, pp. 232101, 2022. [17] X.-D. Wang, K. Vinodgopal, and G.-P. Dai, “Synthesis of carbon nanotubes by catalytic chemical vapor deposition,” Perspective of Carbon Nanotubes, pp. 1-19, 2019. [18] M. Meyyappan, “A review of plasma enhanced chemical vapour deposition of carbon nanotubes,” Journal of Physics D: Applied Physics, vol. 42, no. 21, pp. 213001, 2009. [19] H. B. Abdullah, I. Ramli, I. Ismail, and N. A. Yusof, “Hydrocarbon sources for the carbon nanotubes production by chemical vapour deposition: a review,” Pertanika J Trop Agric Sci, vol. 25, pp. 379-396, 2017. [20] C.-M. Yen, S.-Y. Chang, K.-C. Chen, Y.-J. Feng, L.-H. Chen, B.-Z. Liao, M.-H. Lee, S.-C. Chen, and M.-H. Liao, “The Demonstration of High-Quality Carbon Nanotubes as Through-Silicon Vias (TSVs) for Three-Dimensional Connection Stacking and Power-Via Technology,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1600-1603, Jan. 2022. [21] B.-Z. Liao, L.-H. Chen, K.-C. Chen, H.-Y. Lin, Y.-T. Tsai, T.-W. Chen, Y.-C. Chan, M.-H. Lee, and M.-H. Liao, “Multi-Layer Chips on Wafer Stacking Technologies with Carbon Nano-Tubes as Through-Silicon Vias and it’s potential applications for Power-Via technologies,” in Proc. 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 2022, pp. 1811-1817. [22] Y.-C. Chan, N. Basu, T.-W. Chen, Y.-T. Tsai, H.-Y. Lin, S.-C. Chen, M.-H. Lee, and M.-H. Liao, “The Analysis of Multiwall Carbon Nanotubes as Through Silicon Via by Equivalent Circuit Model at Different Operating Temperatures in Multilayers Stacking Scheme,” IEEE Transactions on Electron Devices, 2023. [23] C. Xu, H. Li, R. Suaya, and K. Banerjee, “Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs,” IEEE Transactions on Electron Devices, vol. 57, no. 12, pp. 3405-3417, Oct. 2010. [24] B. Kim, S. Kannan, A. Gupta, S.-H. Noh, and L. Li, “Characterization of high performance CNT-based TSV for radar applications,” in Proc. 2011 IEEE 13th Electronics Packaging Technology Conference, 2011, pp. 445-449. [25] Y. Feng, and S. L. Burkett, “Modeling a copper/carbon nanotube composite for applications in electronic packaging,” Computational Materials Science, vol. 97, pp. 1-5, 2015. [26] J. Su, R. Ma, X. Chen, L. Han, R. Yang, and W. Zhang, “Low-loss shielded through-silicon vias filled with multi-walled carbon nanotube bundle,” Microelectronics journal, vol. 58, pp. 83-88, 2016. [27] W.-S. Zhao, W.-Y. Yin, X.-P. Wang, and X.-L. Xu, “Frequency-and temperature-dependent modeling of coaxial through-silicon vias for 3-D ICs,” IEEE transactions on electron devices, vol. 58, no. 10, pp. 3358-3368, 2011. [28] X. Chen, L. Qiu, J. Ren, G. Guan, H. Lin, Z. Zhang, P. Chen, Y. Wang, and H. Peng, “Novel electric double‐layer capacitor with a coaxial fiber structure,” Advanced Materials, vol. 25, no. 44, pp. 6436-6441, 2013. [29] E. Bogatin, Signal integrity: simplified: Prentice Hall Professional, 2004. [30] R. Mavaddat, “Network scattering parameters,” 1996. [31] K. C. Chen, N. Basu, S. C. Chen, M. H. Lee, and M. H. Liao, “The Investigation of Electrical Characteristics for Carbon Nano-Tubes as Through Silicon Via in Multi-Layer Stacking Scheme With an Optimized Structure,” IEEE Trans. Electron Devices, vol. 69, no. 9, pp. 5386-5390, Aug. 2022. [32] T.-L. Wu, F. Buesink, and F. Canavero, “Overview of signal integrity and EMC design technologies on PCB: Fundamentals and latest progress,” IEEE transactions on electromagnetic compatibility, vol. 55, no. 4, pp. 624-638, 2013. [33] keysight. "Vector Network Analyzer," Jun., 2023; https://www.keysight.com/tw/zh/solutions/measurement-fundamentals/network-analysis.html. [34] E. Pop, D. Mann, J. Cao, Q. Wang, K. Goodson, and H. Dai, “Negative differential conductance and hot phonons in suspended nanotube molecular wires,” Physical Review Letters, vol. 95, no. 15, pp. 155505, 2005. [35] J. Jiang, R. Saito, A. Grüneis, S. Chou, G. G. Samsonidze, A. Jorio, G. Dresselhaus, and M. Dresselhaus, “Photoexcited electron relaxation processes in single-wall carbon nanotubes,” Physical Review B, vol. 71, no. 4, pp. 045417, 2005. [36] E. Pop, D. Mann, J. Reifenberg, K. Goodson, and H. Dai, “Electro-thermal transport in metallic single-wall carbon nanotubes for interconnect applications,” in Proc. IEDM Tech. Dig., Dec. 2005, pp. 4 pp.-256. [37] A. Naeemi, and J. D. Meindl, “Physical Modeling of Temperature Coefficient of Resistance for Single- and Multi-Wall Carbon Nanotube Interconnects,” IEEE Electron Device Lett., vol. 28, no. 2, pp. 135-138, Jan. 2007. [38] C. T. White, and T. N. Todorov, “Carbon nanotubes as long ballistic conductors,” Nature, vol. 393, no. 6682, pp. 240-242, 1998. [39] J. Jiang, J. Dong, H. Yang, and D. Xing, “Universal expression for localization length in metallic carbon nanotubes,” Physical Review B, vol. 64, no. 4, pp. 045409, 2001. [40] J. Zheng, Z.-Q. Su, G.-Y. Wang, M. Li, W.-S. Zhao, and G. Wang, “Circuit modeling of Cu/CNT composite through-silicon vias (TSV),” in Proc. 2015 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP), Jul. 2015, pp. 1-3. [41] W.-S. Zhao, W.-Y. Yin, and Y.-X. Guo, “Electromagnetic compatibility-oriented study on through silicon single-walled carbon nanotube bundle via (TS-SWCNTBV) arrays,” IEEE Trans. Electromagn. Compat., vol. 54, no. 1, pp. 149-157, Oct. 2011. [42] A. Maffucci, S. A. Maksimenko, G. Miano, and G. Y. Slepyan, “Electrical conductivity of carbon nanotubes: Modeling and characterization,” Carbon Nanotubes for Interconnects: Process, Design and Applications, pp. 101-128, 2017. [43] A. Naeemi, and J. D. Meindl, “Performance Modeling for Single- and Multiwall Carbon Nanotubes as Signal and Power Interconnects in Gigascale Systems,” IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2574-2582, Sep. 2008. [44] A. Naeemi, and J. D. Mein, “Compact physical models for multiwall carbon-nanotube interconnects,” IEEE Electron Device Lett., vol. 27, no. 5, pp. 338-340, May 2006. [45] H. J. Li, W. Lu, J. Li, X. Bai, and C. Gu, “Multichannel ballistic transport in multiwall carbon nanotubes,” Physical review letters, vol. 95, no. 8, pp. 086601, 2005. [46] Y. Saito, T. Yoshikawa, S. Bandow, M. Tomita, and T. Hayashi, “Interlayer spacings in carbon nanotubes,” Phys. Rev. B, vol. 48, no. 3, pp. 1907-1909, Jul. 1993. [47] H. J. Li, W. G. Lu, J. J. Li, X. D. Bai, and C. Z. Gu, “Multichannel Ballistic Transport in Multiwall Carbon Nanotubes,” Phys. Rev. Lett., vol. 95, no. 8, pp. 086601, Aug. 2005. [48] B. Vaisband, A. Maurice, C. W. Tan, B. K. Tay, and E. G. Friedman, “Multi-Bit CNT TSV for 3-D ICs,” in Proc. 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Oct. 2020, pp. 1-5. [49] M. K. Majumder, A. Kumari, B. Kaushik, and S. K. Manhas, “Analysis of crosstalk delay using mixed CNT bundle based through silicon vias,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2014, pp. 441-444. [50] G. Katti, A. Mercha, M. Stucchi, Z. Tokei, D. Velenis, J. Van Olmen, C. Huyghebaert, A. Jourdain, M. Rakowski, and I. Debusschere, “Temperature dependent electrical characteristics of through-si-via (TSV) interconnections,” in Proc. 2010 IEEE International Interconnect Technology Conference, Jun. 2010, pp. 1-3. [51] M. K. Majumder, P. K. Das, and B. K. Kaushik, “Delay and crosstalk reliability issues in mixed MWCNT bundle interconnects,” Microelectronics Reliability, vol. 54, no. 11, pp. 2570-2577, 2014. [52] W. Bao, S. Meguid, Z. Zhu, and G. Weng, “Tunneling resistance and its effect on the electrical conductivity of carbon nanotube nanocomposites,” Journal of Applied Physics, vol. 111, no. 9, pp. 093726, 2012. [53] G. Katti, M. Stucchi, D. Velenis, B. Soree, K. De Meyer, and W. Dehaene, “Temperature-Dependent Modeling and Characterization of Through-Silicon Via Capacitance,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 563-565, Mar. 2011. [54] W.-Y. Yin, K. Kang, and J.-F. Mao, “Electromagnetic-thermal characterization of on on-chip coupled (a) symmetrical interconnects,” IEEE Trans. Adv. Packag., vol. 30, no. 4, pp. 851-863, Nov. 2007. [55] W.-S. Zhao, J. Zheng, F. Liang, K. Xu, X. Chen, and G. Wang, “Wideband Modeling and Characterization of Differential Through-Silicon Vias for 3-D ICs,” IEEE Trans. Electron Devices, vol. 63, no. 3, pp. 1168-1175, Jan. 2016. [56] W.-S. Zhao, Q.-H. Hu, K. Fu, Y.-Y. Zhang, D.-W. Wang, J. Wang, Y. Hu, and G. Wang, “Modeling of Carbon Nanotube-Based Differential Through-Silicon Vias in 3-D ICs,” IEEE Transactions on Nanotechnology, vol. 19, pp. 492-499, Jul. 2020. [57] terasense. "Radio Frequency Bands," Jun., 2023; https://terasense.com/terahertz-technology/radio-frequency-bands/. [58] N. Kim, D. Wu, D. Kim, A. Rahman, and P. Wu, “Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV),” in Proc. 2011 IEEE 61st electronic components and technology conference (ECTC), 2011, pp. 1160-1167. [59] J. Kim, J. S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, and K. Park, “High-frequency scalable electrical model and analysis of a through silicon via (TSV),” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 181-195, Feb. 2011. [60] P. K. Mahanta, P. Adhikari, and K. A. Rocky, “Skin effect analysis for carbon nano material based interconnects at high frequency,” in Proc. 2013 International Conference on Informatics, Electronics and Vision (ICIEV), 2013, pp. 1-6. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91446 | - |
| dc.description.abstract | 在現今的三維積體電路（3DICs）技術中，矽穿孔（Through Silicon Via, TSV）是最重要的關鍵技術，它用於將同質或異質晶片進行垂直方向上的連接。基於先前的研究，奈米碳管（CNTs）因為具有優異的電、熱傳、機械性質而被視為TSV填充材料。然而，奈米碳管TSV的信號傳輸性能非常容易受到工作環境溫度的影響而有所差異。為了評估不同溫度下奈米碳管TSV的電性，需要考慮溫度對於電子平均自由徑（MFP）和奈米碳管導電通道（Conducting Channels）數量。本研究提出了CNTs作為TSV的等效電路模型，並將其電性表現與國際文獻進行基準校正並驗證其正確性。此外，也研究了多壁奈米碳管在不同操作溫度下的多層堆疊系統中的信號完整度，將奈米碳管TSV與傳統銅金屬Cu TSV的進行了電性能比較。結果顯示，當工作溫度在一定範圍內升高時，奈米碳管TSV對於信號傳遞品質會有增加的效果，且隨著溫度的上升，CNTs TSV比Cu TSV具有更多優勢。總結而言，本研究提出更全面的奈米碳管TSV等效電路模型並獲得驗證，同時也證實了奈米碳管在各種環境溫度下皆非常有潛力作為TSV的填充材料。 | zh_TW |
| dc.description.abstract | In nowadays 3-D integrated circuit (3D IC) technology, through silicon via (TSV) is the most important component, which connects homogeneous or heterogeneous dies vertically with each other. Based on our previous research, carbon nanotubes (CNTs) have been considered as TSV filling materials due to their outstanding electrical, thermal, and mechanical properties. However, the operating temperatures would significantly affect the performance of signal transmission in CNTs TSV. To evaluate the electrical characteristics of CNTs TSV with different realistic temperatures, the considerations of temperature-dependent electron mean free path (MFP, λ), and number of conducting channels of CNTs are necessary. In this work, the equivalent circuit model of CNTs as TSV is presented and the simulated electrical behaviors are benchmarked with other literatures. Based on the proposed model, multi-wall (MW) CNTs’ electrical performance in multilayers stacking system under different operating temperatures is investigated.
In addition, we also compare the electrical performance of CNTs as TSV with the conventional filling material, copper (Cu). It shows that CNTs TSV has more advantages than Cu TSV when the operating temperature becomes higher. In summary, the proposed equivalent circuit model in this workis more comprehensive and yields more realistic results. Meanwhile, CNT is a promising material for TSV under varying operation temperatures. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-01-26T16:32:39Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-01-26T16:32:39Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 碩士論文審定書 I
publication list II 致謝 III 中文摘要 IV abstract V 目錄 VII 圖目錄 X 表目錄 XII 第一章 緒論 1 1.1 前言 1 1.2 研究背景與動機 2 1.3 論文架構 5 第二章 文獻回顧與理論基礎 7 2.1 基於TSV的先進封裝技術 7 2.1.1 先進封裝技術發展現況 7 2.1.2 TSV製程技術簡介 10 2.1.3 奈米碳管TSV技術簡介 12 2.2 TSV的等效電路模型 15 2.3 訊號完整度 18 2.3.1 散射參數 18 2.3.2 量測儀器 22 2.4 電子平均自由徑 23 2.5 奈米碳管導電通道 27 2.6 奈米碳管TSV填充數量 32 第三章 多壁奈米碳管TSV模型 35 3.1 奈米碳管TSV結構 35 3.1.1 TSV結構 35 3.1.2 材料選用 36 3.2 等效電路模型 37 3.2.1 模擬方式 37 3.2.2 等效電路圖 40 3.3 等效電子元件設計 42 3.3.1 等效電阻 42 3.3.2 等效電感 44 3.3.3 量子電容 45 3.3.4 絕緣層電容 46 3.3.5 等效矽基板 49 3.4 模型驗證 51 3.4.1 參考文獻 51 3.4.2 驗證結果 52 第四章 多壁奈米碳管TSV信號分析 55 4.1 分析條件 55 4.1.1 取樣頻率 55 4.1.2 取樣溫度 56 4.1.3 評估準則 57 4.2 傳輸頻率分析 59 4.3 工作溫度分析 61 4.4 填充材料分析 63 第五章 研究總結與未來展望 67 5.1. 研究總結 67 5.2. 未來展望 68 參考文獻 70 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 三維積體電路（3D IC） | zh_TW |
| dc.subject | 工作溫度 | zh_TW |
| dc.subject | 等效電路模型 | zh_TW |
| dc.subject | 奈米碳管導電通道數 | zh_TW |
| dc.subject | 矽穿孔（TSV） | zh_TW |
| dc.subject | 奈米碳管（CNTs） | zh_TW |
| dc.subject | 電子平均自由行徑（MFP） | zh_TW |
| dc.subject | CNTs conducting channel | en |
| dc.subject | 3D integrated circuit (3D IC) | en |
| dc.subject | carbon nanotubes (CNTs) | en |
| dc.subject | through silicon via (TSV) | en |
| dc.subject | equivalent circuit model | en |
| dc.subject | temperature | en |
| dc.subject | electron mean free path (MFP) | en |
| dc.title | 多壁奈米碳管矽穿孔技術於溫度變化下的電性研究 | zh_TW |
| dc.title | The Analysis of Multiwall Carbon Nanotubes as Through Silicon Via with Varying Operating Temperatures | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 劉建豪;李敏鴻 | zh_TW |
| dc.contributor.oralexamcommittee | Chien-Hao Liu;Min-Hung Lee | en |
| dc.subject.keyword | 三維積體電路（3D IC）,奈米碳管（CNTs）,矽穿孔（TSV）,等效電路模型,工作溫度,電子平均自由行徑（MFP）,奈米碳管導電通道數, | zh_TW |
| dc.subject.keyword | 3D integrated circuit (3D IC),carbon nanotubes (CNTs),through silicon via (TSV),equivalent circuit model,temperature,electron mean free path (MFP),CNTs conducting channel, | en |
| dc.relation.page | 77 | - |
| dc.identifier.doi | 10.6342/NTU202400034 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2024-01-08 | - |
| dc.contributor.author-college | 工學院 | - |
| dc.contributor.author-dept | 機械工程學系 | - |
| 顯示於系所單位： | 機械工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-112-1.pdf 授權僅限NTU校內IP使用（校園外請利用VPN校外連線服務） | 3.85 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。