請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91386完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | zh_TW |
| dc.contributor.advisor | Tai-Cheng Lee | en |
| dc.contributor.author | 皮牧蘅 | zh_TW |
| dc.contributor.author | Mu-Heng Pi | en |
| dc.date.accessioned | 2024-01-26T16:16:31Z | - |
| dc.date.available | 2024-01-27 | - |
| dc.date.copyright | 2024-01-26 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2024-01-15 | - |
| dc.identifier.citation | [1] R. Walden, “Analog-to-digital converter survey and analysis,” IEEE Journal on Selected Areas in Communications, vol. 17, pp. 539–550, Apr. 1999.
[2] S. Pavan, R. Schreier, and G. C. Temes, Understanding delta-sigma data converters. John Wiley & Sons, 2017. [3] A. M. A. Ali, A. Morgan, C. Dillon, G. Patterson, S. Puckett, P. Bhoraskar, H. Dinc, M. Hensley, R. Stop, S. Bardsley, D. Lattimore, J. Bray, C. Speir, and R. Sneed, “A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 2602–2612, Dec. 2010. [4] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U.K. Moon, “Ring Amplifiers for Switched Capacitor Circuits,” IEEE Journal of Solid-State Circuits, vol. 47, pp. 2928–2942, Dec. 2012. [5] Y. Lim and M. P. Flynn, “A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers,” IEEE Journal of Solid-State Circuits, vol. 50, pp. 2331–2341, Oct. 2015. [6] X. Tang, L. Shen, B. Kasap, X. Yang, W. Shi, A. Mukherjee, D. Z. Pan, and N. Sun, “An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier,” IEEE Journal of Solid-State Circuits, vol. 55, pp. 1011–1022, Apr. 2020. [7] X. Tang, X. Yang, W. Zhao, C.-K. Hsu, J. Liu, L. Shen, A. Mukherjee, W. Shi, S. Li, D. Z. Pan, and N. Sun, “A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier,” IEEE Journal of Solid-State Circuits, vol. 55, pp. 3248–3259, Dec. 2020. [8] X. Tang, X. Yang, J. Liu, W. Shi, D. Z. Pan, and N. Sun, “27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 376–378, Feb. 2021. [9] K. M. Megawer, F. A. Hussien, M. M. Aboudina, and A. N. Mohieldin, “A Systematic Design Methodology for Class-AB-Style Ring Amplifiers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, pp. 1169–1173, Sep. 2018. [10] A. Abo and P. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 599–606, May 1999. [11] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 731–740, Apr. 2010. [12] L. Sumanen, M. Waltari, and K. Halonen, “A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters,” ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445), vol. 1, pp. 32–35, Dec. 2000. [13] J. Lagos, B. Hershberg, E. Martens, P. Wambacq, and J. Craninckx, “A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 54, pp. 403–416, Feb. 2019. [14] J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq, and J. Craninckx, “A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers,” IEEE Journal of Solid-State Circuits, vol. 54, pp. 646–658, Mar. 2019. [15] W. Jiang, Y. Zhu, M. Zhang, C.-H. Chan, and R. P. Martins, “A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier,” IEEE Journal of Solid-State Circuits, vol. 55, pp. 322–332, Feb. 2020. [16] H.-H. Chang, T.-C. Lin, and T.-C. Lee, “A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, pp. 2021–2025, Apr. 2022. [17] B. Murmann, “ADC Performance Survey 1997-2023.” [Online]. Available: https://web.stanford.edu/~murmann/adcsurvey.html, 2023. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91386 | - |
| dc.description.abstract | 本論文將環形放大器與浮接放大器這兩種放大器作結合，成為浮接環形放大器。這種新型放大器也可以達成高速、高線性度，同時因為前二級並無產生靜態電流，消耗的功率僅為普通環形放大器的一半。我們將浮接環形放大器接在MADC中，並實作一個十位元的導管式類比數位轉換器。
本晶片使用台積電28奈米製程下線，總面積為1.57平方毫米。量測中，使用0.9伏特電源，在八億赫茲的取樣頻率下，可測得44.34分貝的訊號對雜訊失真比，同時僅消耗11.56毫瓦。 | zh_TW |
| dc.description.abstract | In this thesis, we combine two ideas, the ring amplifier and the floating amplifier, to be a brand new type floating ring amplifier. The new amplifier can achieve high speed, high linearity while with a 0.5× power consumption compared to traditional ring amplifiers since there is no static current in the first two stages. The proposed amplifier is applied in the multiplying DAC (MDAC) to fulfill a 10-bit pipelined ADC.
The chip is fabricated in a TSMC 28-nm technology and the total area is 1.57 mm2. In measurement, using a 0.9-V supply, the proposed circuit achieves 44.34 dB SNDR at 800 MS/s while consuming 11.56 mW. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-01-26T16:16:31Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-01-26T16:16:31Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 ii
誌謝 iii 摘要 v Abstract vi Contents vii List of Figures x List of Tables xii 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Structure 1 2 Analog-to-Digital Converter Fundamentals 3 2.1 Quantization 3 2.2 Performance Metrics for ADC 5 2.2.1 Resolution Related 5 2.2.2 Speed 6 2.2.3 Power 7 2.2.4 Figure of Merit (FoM) 7 2.3 Pipelined ADC 8 2.3.1 1-bit Stage 8 2.3.2 1.5-bit Stage 9 2.4 Ring Amplifier 10 2.4.1 Slewing Phase 10 2.4.2 Stabilization Phase 11 2.4.3 Steady-State Phase 11 2.5 Floating Amplifier 11 2.6 Conclusion 12 3 System Architecture and Building Blocks 13 3.1 System Overview 13 3.1.1 Sample-and-Hold-less Front-End 14 3.1.2 Multiplying DAC 15 3.1.3 2-bit Flash Back-End Circuit 17 3.2 Floating Ring Amplifier 17 3.2.1 Operation 19 3.2.2 Design 20 3.2.3 Simulation 21 3.2.4 Comparison 22 3.2.5 Common-Mode Feedback 24 3.3 Peripheral Circuits 25 3.3.1 Bootstrapped Switch 25 3.3.2 Comparator 25 3.3.3 Comparator Logic 27 3.3.4 Clock Generator 29 3.3.5 Alignment and Decimation 30 3.4 Simulation Results 32 4 Analysis 34 4.1 Gain Error 34 4.1.1 Finite Amplifier Gain 35 4.1.2 Capacitor Mismatch 35 4.1.3 MDAC Parasitics 37 4.2 MDAC Noise 37 4.3 Comparator Noise and Offset 38 5 Measurement 40 5.1 Printed Circuit Board Design 40 5.2 Die Photo 41 5.3 Measurement Setup 41 5.4 Measurement Result 43 6 Conclusion 47 Bibliography 48 | - |
| dc.language.iso | en | - |
| dc.subject | 浮接式環形放大器 | zh_TW |
| dc.subject | 環形放大器 | zh_TW |
| dc.subject | 浮接放大器 | zh_TW |
| dc.subject | 導管式類比數位轉換器 | zh_TW |
| dc.subject | Floating Ring Amplifier | en |
| dc.subject | Pipelined ADC | en |
| dc.subject | Floating Amplifier | en |
| dc.subject | Ring Amplifier | en |
| dc.title | 使用浮接環形放大器實作的導管式類比數位轉換器 | zh_TW |
| dc.title | A Pipelined ADC with Floating Ring Amplifiers | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳信樹;鍾勇輝;劉深淵 | zh_TW |
| dc.contributor.oralexamcommittee | Hsin-Shu Chen;Yung-Hui Chung;Shen-Iuan Liu | en |
| dc.subject.keyword | 導管式類比數位轉換器,浮接放大器,環形放大器,浮接式環形放大器, | zh_TW |
| dc.subject.keyword | Pipelined ADC,Floating Amplifier,Ring Amplifier,Floating Ring Amplifier, | en |
| dc.relation.page | 50 | - |
| dc.identifier.doi | 10.6342/NTU202303958 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2024-01-16 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
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