一個具有時間基底迴路濾波器及使用注入和背景噪音校正技術之次取樣鎖相迴路

Abstract

本論文實現一個具有小面積之時間基底濾波器的次取樣鎖相迴路。 在這項研究中，我們達到突波以及抖動的降低。藉由使用改良的比例路徑、相位選擇技術及相位拉扯機制，降低了突波；此外，本架構亦採用背景相位噪音校正使得相位拉扯引起的噪音降低。此鎖相迴路採用TSMC 90奈米製程設計，運作於2.4 GHz、200 MHz的參考頻率，模擬的參考突波為-54 dBc，均方根抖動量為0.42 ps，功耗為7.8 mW，FoMJitter為-238.9 dB。

In this thesis, we present the implementation of a Sub-sampling PLL featuring a small area time-based loop filter. Within the confines of this study, we introduce a PLL achieving reduction in spurious signals and jitter. This reduction of the spur is made possible through the utilization of a modified proportional path, a phase selection technique, and a phase pulling mechanism. Furthermore, our implementation incorporates a background phase noise cancellation strategy, mitigating the noise-related consequences associated with the phase pulling process. The overall PLL is designed in TSMC 90-nm CMOS process. Operating at 2.4 GHz and 200 MHz reference frequency, the simulated reference spur level is -54 dBc, the integrated jitter is 0.42 ps with power consumption of 7.8 mW and the corresponding FoMJitter is -238.9 dB.