請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91200完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 彭隆瀚 | zh_TW |
| dc.contributor.advisor | Lung-Han Peng | en |
| dc.contributor.author | 蘇士傑 | zh_TW |
| dc.contributor.author | Shih-Chieh Su | en |
| dc.date.accessioned | 2023-12-12T16:10:48Z | - |
| dc.date.available | 2023-12-13 | - |
| dc.date.copyright | 2023-12-12 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-11-30 | - |
| dc.identifier.citation | [1] Y. Liu, X. Duan, H.-J. Shin, S. Park, Y. Huang, and X. Duan, "Promises and prospects of two-dimensional transistors," Nature, vol. 591, no. 7848, pp. 43-53, Mar 2021.
[2] G. Moore, "Cramming more components onto integrated circuits', Electronics, vol. 38, no. 8," April, vol. 9, pp. 114-117, 1965. [3] K. Rim et al., "Strained Si NMOSFETs for high performance CMOS technology," in 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No. 01 CH37184), 2001: IEEE, pp. 59-60. [4] K. Mistry et al., "A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pbfree packaging," in 2007 IEEE International Electron Devices Meeting, 2007: IEEE, pp. 247-250. [5] M. Van Dal et al., "Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography," in 2007 IEEE symposium on VLSI technology, 2007: IEEE, pp. 110-111. [6] X. Yin et al., "Vertical sandwich gate-all-around field-effect transistors with selfaligned high-k metal gates and small effective-gate-length variation," IEEE Electron Device Letters, vol. 41, no. 1, pp. 8-11, 2019. [7] F. Mayer et al., "Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible tunnel FET performance," in 2008 IEEE International Electron Devices Meeting, 2008: IEEE, pp. 1-5. [8] A. Javey, J. Guo, Q. Wang, M. Lundstrom, and H. Dai, "Ballistic carbon nanotube field-effect transistors," Nature, vol. 424, no. 6949, pp. 654-657, Aug 7 2003. [9] B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti, and A. Kis, "Single-layer MoS2 transistors," Nature Nanotechnology, vol. 6, no. 3, pp. 147-150, Mar 2011. [10] I. Ferain, C. A. Colinge, and J.-P. Colinge, "Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors," Nature, vol. 479, no. 7373, pp. 310-316, Nov 17 2011. [11] M. Chhowalla, D. Jena, and H. Zhang, "Two-dimensional semiconductors for transistors," Nature Reviews Materials, vol. 1, no. 11, pp. 1-15, Nov 2016. [12] Y. Liu, X. Duan, Y. Huang, and X. Duan, "Two-dimensional transistors beyond graphene and TMDCs," Chemical Society Reviews, vol. 47, no. 16, pp. 6388-6409, Aug 13 2018. [13] S. M. Sze, Y. Li, and K. K. Ng, Physics of semiconductor devices. John wiley & sons, 2021. [14] W. Cao et al., "The future transistors," Nature, vol. 620, no. 7974, pp. 501-515, Aug 17 2023. [15] L. Xie et al., "Graphene‐contacted ultrashort channel monolayer MoS2 transistors," Advanced Materials, vol. 29, no. 37, p. 1702522, Oct 2017. [16] S. Das et al., "Transistors based on two-dimensional materials for future integrated circuits," Nature Electronics, vol. 4, no. 11, pp. 786-799, Nov 2021. [17] P. Ajayan, P. Kim, and K. Banerjee, "Two-dimensional van der Waals materials," Physics Today, vol. 69, no. 9, pp. 38-44, Sep 2016. [18] T. Roy et al., "Field-effect transistors built from all two-dimensional material components," ACS Nano, vol. 8, no. 6, pp. 6259-6264, Jun 2014. [19] A. M. Ionescu and H. Riel, "Tunnel field-effect transistors as energy-efficient electronic switches," Nature, vol. 479, no. 7373, pp. 329-337, Nov 17 2011. [20] M. A. Alam, M. Si, and P. D. Ye, "A critical review of recent progress on negative capacitance field-effect transistors," Applied Physics Letters, vol. 114, no. 9, Mar 4 2019. [21] J.-H. Kim, Z. C. Chen, S. Kwon, and J. Xiang, "Steep subthreshold slope nanoelectromechanical field-effect transistors with nanowire channel and back gate geometry," in 71st Device Research Conference, 2013: IEEE, pp. 209-210. [22] K. Gopalakrishnan, R. Woo, C. Jungemann, P. B. Griffin, and J. D. Plummer, "Impact ionization MOS (I-MOS)-part II: experimental results," IEEE Transactions on Electron Devices, vol. 52, no. 1, pp. 77-84, 2004. [23] H. Zhao, Y. Chen, Y. Wang, F. Zhou, F. Xue, and J. Lee, "InGaAs tunneling fieldeffect- transistors with atomic-layer-deposited gate oxides," IEEE Transactions on Electron Devices, vol. 58, no. 9, pp. 2990-2995, Sep 2011. [24] D. Mohata et al., "Barrier-engineered arsenide–antimonide heterojunction tunnel FETs with enhanced drive current," IEEE Electron Device Letters, vol. 33, no. 11, pp. 1568-1570, Nov 2012. [25] A. W. Dey et al., "High-current GaSb/InAs (Sb) nanowire tunnel field-effect transistors," IEEE Electron device letters, vol. 34, no. 2, pp. 211-213, Feb 2013. [26] S. Agarwal and E. Yablonovitch, "Pronounced effect of pn-junction dimensionality on tunnel switch threshold shape," arXiv preprint arXiv:1109.0096, 2011. [27] K. S. Novoselov et al., "Electric field effect in atomically thin carbon films," Science, vol. 306, no. 5696, pp. 666-669, Oct 22 2004. [28] G. Plechinger et al., "A direct comparison of CVD-grown and exfoliated MoS2 using optical spectroscopy," Semiconductor Science and Technology, vol. 29, no. 6, p. 064008, Jun 2014. [29] J. Hong et al., "Exploring atomic defects in molybdenum disulphide monolayers," Nature Communications, vol. 6, no. 1, p. 6293, Feb 19 2015. [30] A. Castellanos-Gomez et al., "Deterministic transfer of two-dimensional materials by all-dry viscoelastic stamping," 2D Materials, vol. 1, no. 1, p. 011002, Jun 2014. [31] S. Masubuchi et al., "Autonomous robotic searching and assembly of twodimensional crystals to build van der Waals superlattices," Nature Communications, vol. 9, no. 1, pp. 1-12, Apr 12 2018. [32] S. Fan et al., "Tunable negative differential resistance in van der Waals heterostructures at room temperature by tailoring the interface," ACS Nano, vol. 13, no. 7, pp. 8193-8201, Jul 2019. [33] J. Henrie, S. Kellis, S. M. Schultz, and A. Hawkins, "Electronic color charts for dielectric films on silicon," Optics express, vol. 12, no. 7, pp. 1464-1469, Apr 5 2004. [34] H. Li et al., "Rapid and reliable thickness identification of two-dimensional nanosheets using optical microscopy," ACS Nano, vol. 7, no. 11, pp. 10344-10353, Nov 26 2013. [35] P. Blake et al., "Making graphene visible," Applied Physics Letters, vol. 91, no. 6, p. 063124, Aug 6 2007. [36] Y. Jung, J. Shen, and J. J. Cha, "Surface effects on electronic transport of 2D chalcogenide thin films and nanostructures," Nano Convergence, vol. 1, no. 1, pp. 1-8, 2014. [37] B. Chakraborty, H. R. Matte, A. Sood, and C. Rao, "Layer‐dependent resonant Raman scattering of a few layer MoS2," Journal of Raman Spectroscopy, vol. 44, no. 1, pp. 92-96, Jan 2013. [38] M.-J. Lee et al., "Thermoelectric materials by using two-dimensional materials with negative correlation between electrical and thermal conductivity," Nature Communications, vol. 7, no. 1, p. 12011, Jun 2016. [39] J. M. Gonzalez and I. I. Oleynik, "Layer-dependent properties of SnS 2 and SnSe 2 two-dimensional materials," Physical Review B, vol. 94, no. 12, p. 125443, 2016. [40] C. Gurnani et al., "Tin (iv) chalcogenoether complexes as single source precursors for the chemical vapour deposition of SnE 2 and SnE (E= S, Se) thin films," Dalton Transactions, vol. 47, no. 8, pp. 2628-2637, 2018. [41] C.-J. Shih, Q. H. Wang, Y. Son, Z. Jin, D. Blankschtein, and M. S. Strano, "Tuning on–off current ratio and field-effect mobility in a MoS2–graphene heterostructure via Schottky barrier modulation," ACS Nano, vol. 8, no. 6, pp. 5790-5798, Jun 2014. [42] D. Sarkar et al., "A subthermionic tunnel field-effect transistor with an atomically thin channel," Nature, vol. 526, no. 7571, pp. 91-95, Oct 1 2015. [43] G. H. Shin, B. Koo, H. Park, Y. Woo, J. E. Lee, and S.-Y. Choi, "Vertical-tunnel field-effect transistor based on a silicon–MoS2 three-dimensional–twodimensional heterostructure," ACS Applied Materials & Interfaces, vol. 10, no. 46, pp. 40212-40218, Nov 21 2018. [44] X. Liu et al., "Modulation of quantum tunneling via a vertical two-dimensional black phosphorus and molybdenum disulfide p–n junction," ACS Nano, vol. 11, no. 9, pp. 9143-9150, Sep 26 2017. [45] X. Yan et al., "Tunable SnSe2/WSe2 heterostructure tunneling field effect transistor," Small, vol. 13, no. 34, p. 1701478, Sep 2017. [46] B. Koo, G. H. Shin, H. Park, H. Kim, and S.-Y. Choi, "Vertical-tunneling fieldeffect transistor based on MoTe2/MoS2 2D–2D heterojunction," Journal of Physics D: Applied Physics, vol. 51, no. 47, p. 475101, Nov 28 2018. [47] K. Nakamura, N. Nagamura, K. Ueno, T. Taniguchi, K. Watanabe, and K. Nagashio, "All 2D heterostructure tunnel field-effect transistors: impact of band alignment and heterointerface quality," ACS Applied Materials & Interfaces, vol. 12, no. 46, pp. 51598-51606, Nov 18 2020. [48] N. Oliva, J. Backman, L. Capua, M. Cavalieri, M. Luisier, and A. M. Ionescu, "WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake," npj 2D Materials and Applications, vol. 4, no. 1, pp. 1-8, Apr 30 2020. [49] S. Kamaei et al., "Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures," npj 2D Materials and Applications, vol. 5, no. 1, p. 76, Sep 7 2021. [50] S. Kim, G. Myeong, J. Park, K. Watanabe, T. Taniguchi, and S. Cho, "Monolayer hexagonal boron nitride tunnel barrier contact for low-power black phosphorus heterojunction tunnel field-effect transistors," Nano Letters, vol. 20, no. 5, pp. 3963-3969, May 13 2020. [51] N. T. Duong et al., "Gate-controlled MoTe2 homojunction for sub-thermionic subthreshold swing tunnel field-effect transistor," Nano Today, vol. 40, p. 101263, Oct 2021. [52] I.-H. Wong, Y.-T. Chen, J.-Y. Yan, H.-J. Ciou, Y.-S. Chen, and C. W. Liu, "Fabrication and low temperature characterization of Ge (110) and (100) p- MOSFETs," IEEE Transactions on Electron Devices, vol. 61, no. 6, pp. 2215- 2219, Jun 2014. [53] Y. Pan et al., "Novel 10-nm gate length MoS2 transistor fabricated on Si fin substrate," IEEE Journal of the Electron Devices Society, vol. 7, pp. 483-488, 2019. [54] H. Zhang et al., "Nucleation and growth mechanisms of Al2O3 atomic layer deposition on synthetic polycrystalline MoS2," The Journal of Chemical Physics, vol. 146, no. 5, Feb 7 2017. [55] P. Zhao et al., "Understanding the impact of annealing on interface and border traps in the Cr/HfO2/Al2O3/MoS2 system," ACS Applied Electronic Materials, vol. 1, no. 8, pp. 1372-1377, Aug 2019. [56] U. E. Avci et al., "Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET," in 2015 IEEE International Electron Devices Meeting (IEDM), 2015: IEEE, pp. 34.5. 1- 34.5. 4. [57] H. Ilatikhameneh, G. Klimeck, J. Appenzeller, and R. Rahman, "Design rules for high performance tunnel transistors from 2-D materials," IEEE Journal of the Electron Devices Society, vol. 4, no. 5, pp. 260-265, Sep 2016. [58] S. Kanungo, G. Ahmad, P. Sahatiya, A. Mukhopadhyay, and S. Chattopadhyay, "2D materials-based nanoscale tunneling field effect transistors: current developments and future prospects," npj 2D Materials and Applications, vol. 6, no. 1, pp. 1-29, Nov 16 2022. [59] J. Knoch and J. Appenzeller, "Modeling of high-performance p-type III–V heterojunction tunnel FETs," IEEE Electron Device Letters, vol. 31, no. 4, pp. 305-307, 2010. [60] M. Van de Put, "Band-to-band tunneling in III-V semiconductor heterostructures," in Eurocon 2013, 2013: IEEE, pp. 2134-2139. [61] F. A. Rasmussen and K. S. Thygesen, "Computational 2D materials database: electronic structure of transition-metal dichalcogenides and oxides," The Journal of Physical Chemistry C, vol. 119, no. 23, pp. 13169-13183, Jun 11 2015. [62] L. Xu et al., "Large‐scale growth and field‐effect transistors electrical engineering of atomic‐layer SnS2," Small, vol. 15, no. 46, p. 1904116, Nov 2019. [63] H. Song et al., "High-performance top-gated monolayer SnS 2 field-effect transistors and their integrated logic circuits," Nanoscale, vol. 5, no. 20, pp. 9666- 9670, 2013. [64] J. Wang et al., "Vertical WS2/SnS2 van der Waals heterostructure for tunneling transistors," Scientific reports, vol. 8, no. 1, pp. 1-9, Dec 10 2018. [65] C. Kim et al., "Fermi level pinning at electrical metal contacts of monolayer molybdenum dichalcogenides," ACS Nano, vol. 11, no. 2, pp. 1588-1596, Feb 2017. [66] X. Cui et al., "Multi-terminal transport measurements of MoS2 using a van der Waals heterostructure device platform," Nature nanotechnology, vol. 10, no. 6, pp. 534-540, Jun 2015, doi: 10.1038/nnano.2015.70. [67] S. Prucnal et al., "Ultra-doped n-type germanium thin films for sensing in the mid infrared," Scientific reports, vol. 6, no. 1, p. 27643, Jun 10 2016. [68] R. N. Sajjad, W. Chern, J. L. Hoyt, and D. A. Antoniadis, "Trap assisted tunneling and its effect on subthreshold swing of tunnel FETs," IEEE Transactions on Electron Devices, vol. 63, no. 11, pp. 4380-4387, Nov 2016. [69] Y. Kang, D. Jeon, and T. Kim, "Local mapping of the thickness-dependent dielectric constant of MoS2," The Journal of Physical Chemistry C, vol. 125, no. 6, pp. 3611-3615, Feb 18 2021. [70] H. Asai, T. Kuroda, K. Fukuda, J. Hattori, T. Ikegami, and N. Mori, "TCAD simulation for transition metal dichalcogenide channel Tunnel FETs consistent with ab-initio based NEGF calculation," in 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2020: IEEE, pp. 93-96. [71] A. Nourbakhsh et al., "MoS2 field-effect transistor with sub-10 nm channel length," Nano Letters, vol. 16, no. 12, pp. 7798-7806, Dec 14 2016. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91200 | - |
| dc.description.abstract | 隨著元件持續微縮，電源電壓與臨界電壓由於次臨界擺幅的熱限制而無法隨之降低，使積體電路的功耗問題愈發嚴峻，為了在室溫下實現次臨界擺幅低於60 mV/dec 的陡峭開關特性，穿隧電晶體因其與超大型積體電路製程的相容性與較低的關閉電流而備受期待，且二維結構的能態密度為階躍函數，二維/三維異質結構被預期能實現比三維結構更陡峭的開關。在本論文中，鍺/二硫化鉬異質接面穿隧電晶體在室溫下具有311 mV/dec 的最低次臨界擺幅，在過驅電壓為2 伏特時具有10^4的開關比；而鍺/二硫化錫異質接面閘極控制二極體則展示了負微分電阻的特性，其峰對谷電流比在-2 伏特的閘極電壓下可達到4.69。
為了實現二維/三維異質接面的對準與堆疊，我們設計並組裝了一套二維材料乾式轉移系統，而透過比較二維材料在光學顯微鏡下的顏色與原子力顯微鏡的厚度掃描結果，二維薄膜在具有100 奈米二氧化矽薄膜的矽基板上顏色對比度與厚度的關係被建立，使二維薄膜的厚度可以透過光學顯微鏡粗略地判定。此外，透過二維材料乾式轉移系統製作的預圖型背閘極二硫化鉬場效電晶體展現了155 mV/dec 的次臨界擺幅與在過驅電壓為2 伏特下具有10^7的開關比。鍺/二硫化鉬穿隧電晶體在常溫下能夠在過驅電壓為2 伏特時達到開關比10^4以及最低次臨界擺幅311 mV/dec，不同閘極氧化層厚度的鍺/二硫化鉬異質接面穿隧電晶體的量測結果確認了縮小閘極氧化層厚度可以有效降低元件的次臨界擺幅，然而氧化層與二維材料間的不完美界面可能是導致次臨界擺幅無法進一步下降的主因。p 型鍺的摻雜濃度也會影響鍺/二硫化鉬異質接面的穿隧機率，進而影響元件表現。鍺/二硫化鉬異質接面穿隧電晶體的變溫量測發現次臨界擺幅不受到溫度的影響，因此主要導通機制應不是熱傳輸，然而，元件中的導通機制是否為帶對帶穿隧效應仍需要進一步的研究與驗證。最後，對二維/三維異質接面穿隧電晶體的TCAD 模擬則展示了降低二維薄膜與閘極氧化層的厚度是優化元件表現的關鍵。 | zh_TW |
| dc.description.abstract | Power consumption becomes a great challenge as transistors are further scaled down since the threshold voltage cannot be reduced due to the limited subthreshold swing (SS) by Boltzmann transport. To achieve steep switching characteristics with SS of sub-60 mV/decade at room temperature, tunnel field-effect transistors (TFETs) are promising owing to their VLSI compatibility and low OFF current. Compared to 3D structures, 2D/3D heterojunction TFETs are expected to have steeper switching because the density of state in 2D structures is a step function. In this work, Ge/MoS2 heterojunction TFETs were fabricated, showing an ON/OFF ratio of 10^4 under an overdrive voltage of 2 V and an SS of 311 mV/decade at room temperature. A Ge/SnS2 gated diode with negative differential resistance (NDR) and a peak-to-valley current ratio (PVCR) of 4.69 is demonstrated.
To achieve precise alignment and stacking of 2D/3D heterojunctions, a dry transfer system for 2D materials is built. By comparing the color of 2D films by optical microscope and the thickness by atomic force microscope on 100-nm SiO2/Si substrates, the color-thickness relationship of 2D films is established. Pre-patterned bottom-gated MoS2 FETs fabricated by the dry transfer system show the best SS of 155 mV/decade and an ON/OFF ratio of 10^7 under an overdrive voltage of 2 V. Ge/MoS2 heterojunction TFETs with an ON/OFF ratio of 10^4 under an overdrive voltage of 2 V and a minimum SS of 311 mV/dec are demonstrated. The results of Ge/MoS2 heterojunction TFETs with different gate oxide thicknesses confirm that reducing oxide thickness can improve the SS. However, the imperfect interface between the gate oxide and 2D films might be the limiting factor for further reduction of SS. The doping level of the p-Ge layer also affects the device performance due to the modulated tunneling probabilities at the Ge/MoS2 heterojunctions. The results of temperature-dependent measurement of Ge/MoS2 heterojunction TFETs show that SS does not change with temperature, which suggests that the dominant transport mechanism is not Boltzmann transport. However, whether the transport in those devices is dominated by the BTBT requires further investigation. Finally, TCAD simulations of 2D/3D heterojunction TFETs are performed and the results suggest that reducing the thickness of 2D films and gate oxide are key factors for further improvement of the device performance. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-12-12T16:10:47Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-12-12T16:10:48Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員會審定書 .......................................................................................................#
誌謝 ................................................................................................................................... i 摘要.................................................................................................................................. ii Abstract............................................................................................................................ iii 目錄...................................................................................................................................v 圖目錄............................................................................................................................ vii 表目錄............................................................................................................................ xii 第 1 章 引言―低功率穿隧電晶體.......................................................................1 1.1 研究動機........................................................................................................1 1.2 二維材料........................................................................................................2 1.3 穿隧電晶體....................................................................................................5 1.4 論文架構........................................................................................................9 第 2 章 二維材料製備與材料分析..................................................................... 11 2.1 二維材料與機械剝離法..............................................................................11 2.2 二維材料的乾式轉移與對準......................................................................13 2.3 二維材料的材料分析..................................................................................17 2.4 二維材料元件的測試分析..........................................................................21 2.5 小結..............................................................................................................24 第 3 章 二維/三維異質接面穿隧電晶體............................................................25 3.1 二維材料穿隧電晶體簡介..........................................................................25 3.2 二維/三維異質接面穿隧電晶體製程流程.................................................30 3.3 二維/三維異質接面穿隧電晶體的室溫電特性.........................................34 3.3.1 氧化層厚度對鍺/二硫化鉬穿隧電晶體元件表現的影響................36 3.3.2 鍺摻雜濃度對鍺/二硫化鉬穿隧電晶體元件表現的影響................39 3.3.3 矽/二硫化鉬、鍺/二硫化鉬與鍺錫/二硫化鉬異質接面電晶體.....42 3.3.4 鍺/二硫化錫異質接面電晶體............................................................44 3.4 二維/三維異質接面穿隧電晶體的變溫量測.............................................48 3.5 鍺/二硫化鉬異質接面穿隧電晶體的TCAD 模擬....................................54 3.6 小結..............................................................................................................57 第 4 章 結論及未來工作.....................................................................................59 4.1 結論..............................................................................................................59 4.2 未來工作......................................................................................................60 參考文獻.........................................................................................................................61 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 二維/三維異質接面 | zh_TW |
| dc.subject | 次臨界擺幅 | zh_TW |
| dc.subject | 穿隧電晶體 | zh_TW |
| dc.subject | 二維/三維異質接面 | zh_TW |
| dc.subject | 二維材料 | zh_TW |
| dc.subject | 次臨界擺幅 | zh_TW |
| dc.subject | 穿隧電晶體 | zh_TW |
| dc.subject | 二維材料 | zh_TW |
| dc.subject | 2D Materials | en |
| dc.subject | 2D/3D heterojunction | en |
| dc.subject | 2D Materials | en |
| dc.subject | Tunnel Field-effect Transistors (TFETs) | en |
| dc.subject | Subthreshold Swing (SS) | en |
| dc.subject | Tunnel Field-effect Transistors (TFETs) | en |
| dc.subject | Subthreshold Swing (SS) | en |
| dc.subject | 2D/3D heterojunction | en |
| dc.title | 二維/三維異質接面穿隧場效電晶體的製作 | zh_TW |
| dc.title | Fabrication of 2D/3D Heterojunction Tunnel Field-effect Transistors | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.coadvisor | 李峻霣 | zh_TW |
| dc.contributor.coadvisor | Jiun-Yun Li | en |
| dc.contributor.oralexamcommittee | 陳奕君;李敏鴻 | zh_TW |
| dc.contributor.oralexamcommittee | I-Chun Cheng;Min-Hung Lee | en |
| dc.subject.keyword | 二維材料,二維/三維異質接面,穿隧電晶體,次臨界擺幅, | zh_TW |
| dc.subject.keyword | 2D Materials,2D/3D heterojunction,Tunnel Field-effect Transistors (TFETs),Subthreshold Swing (SS), | en |
| dc.relation.page | 68 | - |
| dc.identifier.doi | 10.6342/NTU202304462 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2023-11-30 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 光電工程學研究所 | - |
| dc.date.embargo-lift | 2026-11-24 | - |
| 顯示於系所單位： | 光電工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-112-1.pdf 此日期後於網路公開 2026-11-24 | 8.63 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。