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標題: | 處理器抵抗故障注入攻擊之強健與輕量化回復方法 A Robust and Lightweight Recovery Methodology for Processors against Fault Injection Attacks |
作者: | 潘逸軒 Yi-Hsuan Pan |
指導教授: | 黃俊郎 Jiun-Lang Huang |
關鍵字: | 故障注入攻擊,時鐘短時脈衝攻擊,多重連續攻擊,安全處理器,回復, Fault Injection Attack,Clock Glitch,Multiple Glitches Attack,Secure Processor,Recovery, |
出版年 : | 2023 |
學位: | 碩士 |
摘要: | 隨著嵌入式系統在各個領域快速發展及應用,確保其安全性在物聯網的普及下日益重要。嵌入式系統的核心包括微處理器或微控制器,因此處理器的安全性更需加以重視。在處理器面臨的安全挑戰中,故障注入攻擊是其中一個可能遭受的威脅,其能夠通過故障注入攻擊來操縱處理器行為造成系統危害或提取敏感信息,而且故障注入攻擊容易實現且成本低廉。
因此,本論文聚焦於故障注入攻擊,特別探討時鐘故障作為引入故障的手段。時鐘故障會影響目標週期,導致設置時間違規,可能干擾處理器的運作,運行在系統上的軟體安全機制便會不再安全。為了解決這個問題,我們的目標是開發一個安全的處理器,當遭受故障注入攻擊時,能夠抵禦攻擊,並回復至已知且未受攻擊的最後狀態,並在無需重置或關閉的情況下繼續正常運行。 雖然先前的相關研究已經探討了故障注入攻擊的偵測及其對處理器的影響,但少有提出有效的防範措施,且無需大量額外的硬體資源或額外的時間執行。本論文在先前研究的基石上,提出了一種輕量化且強健的安全處理器設計,包括時鐘故障偵測器、處理器架構和額外的回復電路。該回復機制僅基於硬體,無需軟體協助,並且能夠抵禦多個故障攻擊,同時考慮控制危障和資料危障問題。 With the rapid development and widespread application of embedded systems in various domains, ensuring their security has become increasingly critical in the era of the Internet of Things. The core of embedded systems is microprocessors or microcontrollers, making processor security a critical concern. Among the security challenges faced by processors, fault injection attacks (FIA) pose a significant threat, manipulating processor behavior to compromise system integrity and extract sensitive information, and FIAs are relatively easy to implement and cost-effective. This thesis focuses on FIA and, in particular, explores clock glitches as a means of injecting faults. Clock glitch affects targeted cycles, leading to setup time violations and potentially disrupting processor operations. To address this issue, the objective is to develop a secure processor that can withstand FIA, recover from the attack, and continue normal operation without the need for a reset or shutdown. While previous studies have investigated detecting FIA and its impact on processors, few have proposed effective countermeasures without excessive redundancies or additional timing execution. This thesis builds on previous work, proposing a lightweight and robust secure processor design that includes a clock glitch detector, processor architecture, and additional recovery circuits. The recovery mechanism is purely hardware-based, eliminating the need for software assistance, and capable of defending against multiple glitches attacks while considering control and data hazard issues. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/90771 |
DOI: | 10.6342/NTU202302978 |
全文授權: | 未授權 |
顯示於系所單位: | 電機工程學系 |
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