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| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 陳耀銘 | zh_TW |
| dc.contributor.advisor | Yaow-Ming Chen | en |
| dc.contributor.author | 劉志誠 | zh_TW |
| dc.contributor.author | Chih-Cheng Liu | en |
| dc.date.accessioned | 2023-10-03T16:41:14Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-10-03 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-08-08 | - |
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Xu, "Analysis of the Phase-Shifted Carrier Modulation for Modular Multilevel Converters," in IEEE Transactions on Power Electronics, vol. 30, no. 1, pp. 297-310, Jan. 2015. [33] N. Yousefpoor, S. H. Fathi, N. Farokhnia, and H. A. Abyaneh, "THD Minimization Applied Directly on the Line-to-Line Voltage of Multilevel Inverters," in IEEE Transactions on Industrial Electronics, vol. 59, no. 1, pp. 373-380, Jan. 2012. [34] G. J. Capella, J. Pou, S. Ceballos, G. Konstantinou, J. Zaragoza, and V. G. Agelidis, "Enhanced Phase-Shifted PWM Carrier Disposition for Interleaved Voltage-Source Inverters," in IEEE Transactions on Power Electronics, vol. 30, no. 3, pp. 1121-1125, March 2015. [35] E. L. Soares, L. F. M. de Lucena, N. Rocha, C. B. Jacobina, and E. R. C. da Silva, "Enhanced Phase-Shifted Carrier PWM Applied to 3-Phase Multilevel Coupled Inductors Inverters," 2019 IEEE 15th Brazilian Power Electronics Conference and 5th IEEE Southern Power Electronics Conference (COBEP/SPEC), 2019, pp. 1-6. [36] B. P. McGrath and D. G. Holmes, "Multicarrier PWM strategies for multilevel inverters," in IEEE Transactions on Industrial Electronics, vol. 49, no. 4, pp. 858-867, Aug. 2002. [37] R. Naderi and A. Rahmati, "Phase-Shifted Carrier PWM Technique for General Cascaded Inverters," in IEEE Transactions on Power Electronics, vol. 23, no. 3, pp. 1257-1269, May 2008. [38] J. Lee, K. Lee, and Y. Ko, "An improved phase-shifted PWM method for a three-phase cascaded H-bridge multi-level inverter," 2017 IEEE Energy Conversion Congress and Exposition (ECCE), 2017, pp. 2100-2105. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/90572 | - |
| dc.description.abstract | 在傳統橋式電路架構的換流器中，比較難直接運用在中高壓的高功率應用，其最主要原因就是受到半導體元件本身的耐壓及耐流不足。然而透過多相多階式換流器能夠改善原本半導體元件耐壓及耐流不足的問題。而本論文採用的二極體箝位型多階式換流器(Diode-Clamped Multilevel Inverter)具有只需單一電壓源且電路架構簡單的優點。然而因為PCB電路板上的寄生電感以及元件封裝引腳的寄生電感，會造成上下臂開關的電壓分壓不均，導致錯估電壓餘裕而造成開關損壞。本論文主要在針對二極體箝位型換流器受寄生電感的因素，造成開關電壓不平衡的分析，並且推導出包含寄生電感電路架構的數學模型。透過數學模型分析出兩種不同策略可以有效改善開關電壓上不平衡問題，並透過simplis模擬軟體加以驗證。最後透過實作一組5kVA換流器原型機的實測，驗證本論文提出的數學模型及電壓平衡改善策略的正確性。 | zh_TW |
| dc.description.abstract | The conventional full-bridge DC-AC inverter can not be directly applied to medium or high voltage high-power applications due to insufficient voltage and current ratings of the semiconductor power switches. Therefore, different multi-level and multi-phase circuit topologies have been developed to solve the issue of insufficient voltage and current ratings. This thesis adopts the diode-clamped multi-level inverter which has the advantages of single voltage source requirement and circuit simplicity. However, the diode-clamped multi-level inverter suffers from the unbalanced voltage stress on the power switches due to parasitic inductors on the printed circuit board or the device package. The unbalanced voltage can easily damage power switches due to misjudging the device’s voltage rating.
The objective of this thesis is to analyze the impact of the parasitic inductors to the unbalanced switch voltages of the diode-clamped inverter. The mathematical models of the diode-clamped multi-level inverter with parasitic inductors are derived first. Then, two strategies that can effectively reduce the unbalanced voltage are proposed. The effectiveness of the derived mathematical models and the proposed strategies is verified by using the Simplis simulation software. Finally, hardware experimental results from a 5kVA prototype validate the correctness of the derived mathematical models and the performance of the proposed voltage-balancing strategies. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-10-03T16:41:14Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-10-03T16:41:14Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 I
致謝 II 摘要 III ABSTRACT IV 目錄 V 圖目錄 VIII 表目錄 XII 第一章 緒論 1 1-1研究背景與動機 1 1-2文獻回顧 2 1-3章節摘要 3 第二章 多相多階市電併聯換流器 4 2-1併網型換流器 4 2-2多階式換流器電路分析及調變方法 6 2-2.1二極體箝位型換流器電路架構 8 2-2.2多載波正弦脈波寬度調變(Multicarrier SPWM) 8 2-2.3二極體箝位型換流器電路分析 10 2-3多相多階式換流器電路架構及調變方式 12 2-3.1多相多階式換流器電路架構 12 2-3.2交錯式相移脈波寬度調變(PS-PWM) 14 2-3.3多相電壓耦合電路 14 2-4三相電流控制 16 2-4.1直交軸轉換 17 2-4.2三相電流控制迴路 18 2-4.3鎖相迴路 19 第三章 開關電壓不平衡分析與改善 21 3-1有寄生元件之多相多階式換流器 21 3-1.1電路模型 22 3-1.2電路開關電壓不平衡分析 23 3-1.3電路開關不平衡改善 30 3-2電腦模擬驗證 34 3-2.1多相多階式換流器電壓 34 3-2.2 橋臂電流平衡 36 3-2.3開關不平衡電壓改善 41 第四章 硬體電路與軟體控制 48 4-1硬體電路設計 48 4-1.1功率級電路 48 4-1.2控制級電路 51 4-2數位控制程式撰寫 55 4-2.1系統主程式 55 4-2.2中斷副程式 58 4-3模組化電路設計 61 第五章 實作驗證 63 5-1實作電路與實驗設置 63 5-2多相多階換流器電壓測試 64 5-3橋臂電流平衡測試 66 5-4開關電壓平衡測試 70 5-5併網測試 76 第六章 結論與未來展望 78 6-1結論 78 6-2未來展望 79 目錄 80 A.添加開關導通電阻電路模型 80 參考文獻 82 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 寄生元件分析 | zh_TW |
| dc.subject | 開關電壓不平衡 | zh_TW |
| dc.subject | 併網換流器 | zh_TW |
| dc.subject | 二極體箝位型換流器 | zh_TW |
| dc.subject | Diode-clamped inverter | en |
| dc.subject | grid-tied inverter | en |
| dc.subject | unbalanced switch voltages | en |
| dc.subject | parasitic components | en |
| dc.title | 多相多階併網換流器之開關電壓不平衡改善 | zh_TW |
| dc.title | Improvement of Switching Voltage Imbalance for Multiphase-Multilevel Grid -Tied Inverters | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 楊士進;陳景然;張淵智 | zh_TW |
| dc.contributor.oralexamcommittee | Shih-Chin Yang;Ching-Jan Chen;Yuan-Chih Chang | en |
| dc.subject.keyword | 二極體箝位型換流器,併網換流器,開關電壓不平衡,寄生元件分析, | zh_TW |
| dc.subject.keyword | Diode-clamped inverter,grid-tied inverter,unbalanced switch voltages,parasitic components, | en |
| dc.relation.page | 86 | - |
| dc.identifier.doi | 10.6342/NTU202303284 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2023-08-10 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電機工程學系 | - |
| dc.date.embargo-lift | 2028-08-08 | - |
| Appears in Collections: | 電機工程學系 | |
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| File | Size | Format | |
|---|---|---|---|
| ntu-111-2.pdf Restricted Access | 7.06 MB | Adobe PDF | View/Open |
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