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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂良鴻 | zh_TW |
| dc.contributor.advisor | Liang-Hung Lu | en |
| dc.contributor.author | 范芳瑜 | zh_TW |
| dc.contributor.author | Fang-Yu Fan | en |
| dc.date.accessioned | 2023-09-11T16:22:52Z | - |
| dc.date.available | 2025-04-01 | - |
| dc.date.copyright | 2023-09-11 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-03-13 | - |
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Sanchez-Sinencio, "CMOS transconductance multipliers: A tutorial," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 12, pp. 1550-1563, 1998. [26] H. Song, D. Liu, Y. Zhang, W. Rhee, and Z. Wang, "A 6.5–8.1-GHz Communication/Ranging VWB Transceiver for Secure Wireless Connectivity With Enhanced Bandwidth Efficiency and $\Delta\Sigma$ Energy Detection," IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 219-232, 2020, doi: 10.1109/JSSC.2019.2953828. [27] N. Cho, L. Yan, J. Bae, and H.-J. Yoo, "A 60 kb/s–10 Mb/s adaptive frequency hopping transceiver for interference-resilient body channel communication," IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 708-717, 2009. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89587 | - |
| dc.description.abstract | 隨著科技快速的發展，分散式運算的技術逐漸的被應用在各種系統中，以應付大量計算或分析資料的需求。而如今的資料傳遞介面，如單晶片系統(SoC)、單晶片多核系統(Multiprocessor SoC)、晶片上網路(NoC)…等，皆是透過複雜的實體金屬走線實現元件之間的資料傳遞。但是隨著系統日益複雜化、元件數量的不斷增加，系統內部的資料傳遞網路，在硬體的實現上也將面臨佈線困難的瓶頸，如此一來更是限制了系統的可擴張性。
為克服資料傳遞網絡龐大複雜的佈線所帶來的瓶頸，本論文提出了一種適用於分散式運算之平行傳輸技術。所提出的技術概念是在系統中所有的元件上，配備一個傳輸器與接收器，並透過共用的傳輸線，使搭載在這條傳輸線上所有的元件能夠相互傳輸資料，形成一個晶片內部的資料傳遞網路。藉由這條共用傳輸線，替代傳統端口到端口的專用金屬佈線，解決了金屬走線佈局的瓶頸、增加了整個系統的可擴張性與可重新配置性，同時，也實現了一種新穎應用的資料傳遞技術。 本論文研究兩種傳輸系統的實現方法。分別以開關調變(OOK)與相移調變(PSK)，實現兩種非同調的傳輸系統。以分頻多工、direct down-conversion的傳輸與解調方式，以及IQ path接收器架構，實現了第一版的OOK非同調傳輸系統，然而在量測結果中，但所測得之BER並不佳。為了解決這個缺陷，在第二版的系統設計中改採用PSK調變的調變方式，實現了PSK非同調傳輸系統，在量測結果中顯示，此非同調傳輸系統的架構，在BER<10-9的條件下，可運行的頻寬為0.5 GHz–1.4 GHz、最高傳輸速度達到25 Mbps、極限鄰道間距達90 MHz。最終版本的系統設計，改善了第一版本設計中，量測到BER較差的缺陷，並且實現了一種新穎應用的平行資料傳輸系統。 | zh_TW |
| dc.description.abstract | With the rapid development of technology, distributed computing are gradually applied to systems to meet the needs of massive computing or data analysis. Nowadays, data transmission interfaces such as system-on-chip (SoC), multiprocessor system-on-chip (Multiprocessor-SoC), network-on-chip (NoC), etc., are intuitively implemented by port-to-port metal wiring. However, with the growing scale of the system and the increasing number of computing devices, the implementation of the data transmission network encounters the bottleneck of complex wiring. In this case, the scalability of the system is limited.
In order to overcome the bottleneck caused by the massive wiring of the transmission network, this thesis presents a parallel data transmission system for distributed computing. The concept of this system is to enable all the computing devices which are connected to the common transmission line could send and receive data to each other. This common transmission line replaces the physical metal traces from port to port, solving the bottleneck of complex wiring and increasing the scalability of the overall system. As a result, a new type of transmission network is realized. This thesis presents the implementations of two transmission systems. These two systems are realized by using two different modulations, on-off keying (OOK) and phase-shift keying (PSK), respectively. The first chip version of the OOK non-coherent transmission system was implemented by using frequency-division multiplexing (FDM), direct down-conversion demodulation, and IQ paths receiver architecture. In the measurement results, although the receiver did successfully receive and demodulate the signal, the measured BER was not performing well. In order to solve this defect, the problem was analyzed, and the PSK modulation method was adopted in the second system chip, thus realizing a PSK non-coherent transmission system. The measurement results showed that the architecture of this non-coherent transmission system could operate within the bandwidth of 0.5 GHz–1.4 GHz, the maximum data rate was up to 25 Mbps, and a minimum neighbor channel distance of 90 MHz under the condition of BER<10-9. The measurement results show that the final version of the system improves the poorly measured BER of the first version and implements a novel parallel data transmission system. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-09-11T16:22:52Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-09-11T16:22:52Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 ii
摘要 iii Abstract iv Content vi List of Figures iv List of Tables xv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Application 4 1.3 Thesis Organization 5 Chapter 2 Background 6 2.1 System Architecture 6 2.2 Multiple Access Techniques 7 2.2.1 Time-Division Multiple Access (TDMA) 8 2.2.2 Code-Division Multiple Access (CDMA) 9 2.2.3 Frequency-Division Multiple Access (FDMA) 10 2.3 Transmission Method 11 2.3.1 Modulation Scheme 11 2.3.2 Frequency-Division Multiplexing (FDM) 13 2.3.3 Direct Down-conversion 13 2.4 Non-Coherent Transmission 14 2.4.1 Coherent Transmission 14 2.4.2 Non-Coherent Transmission 16 Chapter 3 OOK Non-Coherent Transmission 19 3.1 System Architecture 19 3.2 System Analyze 20 3.2.1 Self-multiplexing 21 3.2.2 IQ Path 22 3.3 Circuit Implementation 25 3.3.1 Transmitter 25 3.3.2 Receiver 29 3.3.2.1 Down-convert Mixer & Self-multiplexing Mixer 29 3.3.2.2 Low-pass Filter 31 3.3.2.3 Comparator 33 3.3.3 Transmission Line (TL) 34 3.3.3.1 Bias Network 34 3.3.3.2 EM Simulation of Transmission Line 35 3.4 Measurement 37 3.5 Brief Summary 42 Chapter 4 PSK Non-Coherent Transmission 45 4.1 System Architecture 45 4.2 System Analyze 46 4.2.1 Transmitter 47 4.2.2 Receiver 49 4.2.2.1 I Path 49 4.2.2.2 Q path 50 4.3 Circuit Implementation 52 4.3.1 Transmitter 52 4.3.2 Receiver 54 4.3.2.1 Down-convert Mixer 55 4.3.2.2 Low-Pass Filter 58 4.3.2.3 Analog One-bit-delay Circuit 60 4.3.2.4 Unity Gain Buffer 61 4.3.2.5 Self-multiplexing Mixer 63 4.3.2.6 Comparator 66 4.3.2.7 IQ phase generator 68 4.3.3 Transmission Line (TL) 69 4.4 Measurement 71 4.4.1 Measurement of Single Channel 72 4.4.2 Measurement of Multiple Channel 79 4.5 Brief Summary 82 Chapter 5 Conclusion 83 5.1 Comparison Table 83 5.2 Conclusion 84 Reference 85 | - |
| dc.language.iso | en | - |
| dc.subject | 相移調變 | zh_TW |
| dc.subject | 平行資料傳輸 | zh_TW |
| dc.subject | 非同調資料傳輸系統 | zh_TW |
| dc.subject | 分頻多工 | zh_TW |
| dc.subject | 開關調變 | zh_TW |
| dc.subject | phase-shift keying | en |
| dc.subject | on-off keying | en |
| dc.subject | non-coherent data transmission system | en |
| dc.subject | parallel data transmission | en |
| dc.subject | frequency-division multiplexing | en |
| dc.title | 適用於分散式運算之平行資料傳輸技術 | zh_TW |
| dc.title | Parallel Data Transmission Technology Suitable for Distributed Computing | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 林宗賢;陳巍仁 | zh_TW |
| dc.contributor.oralexamcommittee | Tsung-Hsien Lin;Wei-Zen Chen | en |
| dc.subject.keyword | 平行資料傳輸,非同調資料傳輸系統,分頻多工,開關調變,相移調變, | zh_TW |
| dc.subject.keyword | parallel data transmission,non-coherent data transmission system,frequency-division multiplexing,on-off keying,phase-shift keying, | en |
| dc.relation.page | 87 | - |
| dc.identifier.doi | 10.6342/NTU202300663 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2023-03-14 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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