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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李建模 | zh_TW |
dc.contributor.advisor | Chien-Mo Li | en |
dc.contributor.author | 陳心屏 | zh_TW |
dc.contributor.author | Xin-Ping Chen | en |
dc.date.accessioned | 2023-08-16T16:43:18Z | - |
dc.date.available | 2023-11-09 | - |
dc.date.copyright | 2023-08-16 | - |
dc.date.issued | 2023 | - |
dc.date.submitted | 2023-08-08 | - |
dc.identifier.citation | M. Abramovici, M. A. Breuer, A. D. Friedman, et al. Digital systems testing and testable design, volume 2. Computer science press New York, 1990.
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89002 | - |
dc.description.abstract | 我們提出測試壓縮技術以降低神經形態晶片的測試時間 (測試配置以及測試樣本)。我們的測試壓縮技術包括動態測試壓縮以及靜態測試壓縮。動態測試壓縮利用機器學習來生成測試配置。靜態測試壓縮在雙樣本霍特林T平方測試的顯著水準限制下降低測試長度。在兩個神經形態架構的實驗結果表明,我們提出的技術可以降低90.44%的總測試配置,以及93.47%的總測試長度。我們的運行時間比先前的方法快了十倍以上。我們所提出的技術不受限於神經形態晶片的應用。 | zh_TW |
dc.description.abstract | We propose test compression techniques to reduce the test time (test configurations and test length) for neuromorphic chips. Our test compression techniques include Dynamic Test Compression (DTC) and Static Test Compression (STC). DTC generates test configurations with machine learning. STC reduces test length under the constraint of the significance level in Two-sample Hotelling’s T-Square Test. Experiments on two neuromorphic architectures show that our proposed techniques can reduce the total test configurations by 90.44% and the total test length by 93.47%, respectively. Our run time is more than 10x faster than the previous method. The proposed techniques are independent of neuromorphic chips’ applications. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-08-16T16:43:18Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2023-08-16T16:43:18Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | 口試委員審定書 i
致謝 ii 摘要 iii Abstract iv Contents v List of Figures viii List of Tables xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed techniques 4 1.3 Contributions 6 1.4 Organization 7 Chapter 2 Background 8 2.1 Neuromorphic chips 8 2.2 Fault model 10 2.3 Previous works 12 2.4 Statistical hypothesis testing 16 2.4.1 Introduction of hypothesis testing 16 2.4.2 Two-sample Hotelling’s T-Square Test 21 Chapter 3 Proposed Techniques 24 3.1 Overall flow 24 3.2 Fault detection with hypothesis testing 25 3.3 Fault dropping with contribution accumulation 27 3.4 Dynamic Test Compression (DTC) 30 3.5 Test pattern generation 33 3.6 Static Test Compression (STC) 34 Chapter 4 Experimental Results 37 4.1 Experimental setup 37 4.2 Test repetition determination 38 4.3 Test compression results 39 Chapter 5 Conclusion 43 References 44 Appendix A — Fault Detection Probability 50 A.1 Fault simulation time 50 A.2 Average fault detection probability 51 Appendix B — Example of Two-sample Hotelling’s T-Square Test 53 | - |
dc.language.iso | en | - |
dc.title | 神經形態晶片的測試壓縮 | zh_TW |
dc.title | Test Compression for Neuromorphic Chips | en |
dc.type | Thesis | - |
dc.date.schoolyear | 111-2 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 黃俊郎;呂學坤 | zh_TW |
dc.contributor.oralexamcommittee | Jiun-Lang Huang;Shyue-Kung Lu | en |
dc.subject.keyword | 神經形態晶片,脈衝神經網路,動態測試壓縮,靜態測試壓縮,測試樣本生成, | zh_TW |
dc.subject.keyword | neuromorphic chip,Spiking Neural Network,dynamic test compression,static test compression,test pattern generation, | en |
dc.relation.page | 57 | - |
dc.identifier.doi | 10.6342/NTU202303828 | - |
dc.rights.note | 同意授權(全球公開) | - |
dc.date.accepted | 2023-08-10 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
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