請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89002完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模 | zh_TW |
| dc.contributor.advisor | Chien-Mo Li | en |
| dc.contributor.author | 陳心屏 | zh_TW |
| dc.contributor.author | Xin-Ping Chen | en |
| dc.date.accessioned | 2023-08-16T16:43:18Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-08-16 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-08-08 | - |
| dc.identifier.citation | M. Abramovici, M. A. Breuer, A. D. Friedman, et al. Digital systems testing and testable design, volume 2. Computer science press New York, 1990.
P. Blouw, X. Choo, E. Hunsberger, and C. Eliasmith. Benchmarking keyword spotting efficiency on neuromorphic hardware. In Proceedings of the 7th annual neuro-inspired computational elements workshop, pages 1–8, 2019. M. P. Chandra et al. On the generalised distance in statistics. In Proceedings of the National Institute of Sciences of India, volume 2, pages 49–55, 1936. I.-W. Chiu, X.-P. Chen, J. S.-I. Hu, and J. C.-M. Li. Automatic test configuration and pattern generation (atcpg) for neuromorphic chips. In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, pages 1–7, 2022. M. Davies, N. Srinivasa, T.-H. Lin, G. Chinya, Y. Cao, S. H. Choday, G. Dimou, P. Joshi, N. Imam, S. Jain, et al. Loihi: A neuromorphic manycore processor with on-chip learning. Ieee Micro, 38(1):82–99, 2018. E. P. Frady, G. Orchard, D. Florey, N. Imam, R. Liu, J. Mishra, J. Tse, A. Wild, F. T. Sommer, and M. Davies. Neuromorphic nearest neighbor search using intel’s pohoiki springs. In Proceedings of the 2020 Annual Neuro-Inspired Computational Elements Workshop, pages 1–10, 2020. A. Gebregiorgis and M. B. Tahoori. Testing of neuromorphic circuits: Structural vs functional. In 2019 IEEE International Test Conference (ITC), pages 1–10. IEEE, 2019. Y.-Z. Hsieh, H.-Y. Tseng, I.-W. Chiu, and J. C. M. Li. Fault modeling and testing of spiking neural network chips. In 2021 IEEE International Test Conference in Asia (ITC-Asia), pages 1–6. IEEE, 2021. D. Ivanov, A. Chezhegov, M. Kiselev, A. Grunin, and D. Larionov. Neuromorphic artificial intelligence systems. Frontiers in Neuroscience, 16:1513, 2022. A. P. Johnson, J. Liu, A. G. Millard, S. Karim, A. M. Tyrrell, J. Harkin, J. Timmis, L. J. McDaid, and D. M. Halliday. Homeostatic fault tolerance in spiking neural networks: a dynamic hardware perspective. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(2):687–699, 2017. R. A. Johnson, D. W. Wichern, et al. Applied multivariate statistical analysis. 2002. N. P. Jouppi, D. H. Yoon, M. Ashcraft, M. Gottscho, T. B. Jablin, G. Kurian, J. Laudon, S. Li, P. Ma, X. Ma, et al. Ten lessons from three generations shaped google＇s tpuv4i: Industrial product. In 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), pages 1–14. IEEE, 2021. N. P. Jouppi, C. Young, N. Patil, and D. Patterson. A domain-specific architecture for deep neural networks. Communications of the ACM, 61(9):50–59, 2018. I. Kataeva, S. Ohtsuka, H. Nili, H. Kim, Y. Isobe, K. Yako, and D. Strukov. Towards the development of analog neuromorphic chip prototype with 2.4 m integrated memristors. In 2019 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–5. IEEE, 2019. D. P. Kingma and J. Ba. Adam: A method for stochastic optimization. arXiv preprint arXiv:1412.6980, 2014. Y. LeCun. The mnist database of handwritten digits. http://yann. lecun. com/exdb/mnist/, 1998. P. Lichtsteiner, C. Posch, and T. Delbruck. A 128× 128 120 db 15 µs latency asynchronous temporal contrast vision sensor. IEEE Journal of Solid-State Circuits, 43(2):566–576, 2008. D. Liu, H. Yu, and Y. Chai. Low-power computing with neuromorphic engineering. Advanced Intelligent Systems, 3(2):2000150, 2021. D. Marković, A. Mizrahi, D. Querlioz, and J. Grollier. Physics for neuromorphic computing. Nature Reviews Physics, 2(9):499–510, 2020. H. Markram. The human brain project. Scientific American, 306(6):50–55, 2012. D. C. Montgomery and G. C. Runger. Applied statistics and probability for engineers. 1994. S. Moradi, N. Qiao, F. Stefanini, and G. Indiveri. A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (dynaps). IEEE transactions on biomedical circuits and systems, 12(1):106–122, 2017. D. Moussa, M. Hefenbrock, C. Münch, and M. Tahoori. Automatic test pattern generation and compaction for deep neural networks. In Proceedings of the 28th Asia and South Pacific Design Automation Conference, pages 436–441, 2023. A. Nallathambi, S. Sen, A. Raghunathan, and N. Chandrachoodan. Probabilistic spike propagation for efficient hardware implementation of spiking neural networks. Frontiers in Neuroscience, 15:694402, 2021. E. Painkras, L. A. Plana, J. Garside, S. Temple, F. Galluppi, C. Patterson, D. R. Lester, A. D. Brown, and S. B. Furber. Spinnaker: A 1-w 18-core system-on-chip for massively-parallel neural network simulation. IEEE Journal of Solid-State Circuits, 48(8):1943–1953, 2013. R. Penrose. A generalized inverse for matrices. In Mathematical proceedings of the Cambridge philosophicalsociety, volume 51, pages 406–413. Cambridge University Press, 1955. R. E. Schumacker. Using R with multivariate statistics. Sage Publications, 2015. A. Sebastian, M. Le Gallo, R. Khaddam-Aljameh, and E. Eleftheriou. Memory devices and applications for in-memory computing. Nature nanotechnology, 15(7):529–544, 2020. P. Stoliar, J. Tranchant, B. Corraze, E. Janod, M.-P. Besland, F. Tesler, M. Rozenberg, and L. Cario. A leaky-integrate-and-fire neuron analog realized with a mott insulator. Advanced Functional Materials, 27(11):1604740, 2017. SynSense. DYNAP-CNN. https://www.synsense.ai/products/dynap-cnn/. C. Szegedy, W. Zaremba, I. Sutskever, J. Bruna, D. Erhan, I. Goodfellow, and R. Fergus. Intriguing properties of neural networks. arXiv preprint arXiv:1312.6199, 2013. H.-Y. Tseng, I.-W. Chiu, M.-T. Wu, and J. C.-M. Li. Machine learning-based test pattern generation for neuromorphic chips. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), pages 1–7, 2021. R. E. Walpole, R. H. Myers, S. L. Myers, and K. Ye. Probability and statistics for engineers and scientists, volume 5. Macmillan New York, 1993. Y. Wu, L. Deng, G. Li, J. Zhu, Y. Xie, and L. Shi. Direct training for spiking neural networks: Faster, larger, better. In Proceedings of the AAAI Conference on Artificial Intelligence, volume 33, pages 1311–1318, 2019. Z. Yan, X. S. Hu, and Y. Shi. Computing-in-memory neural network accelerators for safety-critical systems: Can small device variations be disastrous? In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, pages 1–9, 2022. K.-C. Yang, M.-T. Lee, C.-H. Wu, and J. C.-M. Li. Atpg and test compression for probabilistic circuits. In 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pages 1–4. IEEE, 2019. Y. Zhu, Y. Zhu, H. Mao, Y. He, S. Jiang, L. Zhu, C. Chen, C. Wan, and Q. Wan. Recent advances in emerging neuromorphic computing and perception devices. Journal of Physics D: Applied Physics, 55(5):053002, 2021. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89002 | - |
| dc.description.abstract | 我們提出測試壓縮技術以降低神經形態晶片的測試時間 (測試配置以及測試樣本)。我們的測試壓縮技術包括動態測試壓縮以及靜態測試壓縮。動態測試壓縮利用機器學習來生成測試配置。靜態測試壓縮在雙樣本霍特林T平方測試的顯著水準限制下降低測試長度。在兩個神經形態架構的實驗結果表明，我們提出的技術可以降低90.44%的總測試配置，以及93.47%的總測試長度。我們的運行時間比先前的方法快了十倍以上。我們所提出的技術不受限於神經形態晶片的應用。 | zh_TW |
| dc.description.abstract | We propose test compression techniques to reduce the test time (test configurations and test length) for neuromorphic chips. Our test compression techniques include Dynamic Test Compression (DTC) and Static Test Compression (STC). DTC generates test configurations with machine learning. STC reduces test length under the constraint of the significance level in Two-sample Hotelling’s T-Square Test. Experiments on two neuromorphic architectures show that our proposed techniques can reduce the total test configurations by 90.44% and the total test length by 93.47%, respectively. Our run time is more than 10x faster than the previous method. The proposed techniques are independent of neuromorphic chips’ applications. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-08-16T16:43:18Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-08-16T16:43:18Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 i
致謝 ii 摘要 iii Abstract iv Contents v List of Figures viii List of Tables xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed techniques 4 1.3 Contributions 6 1.4 Organization 7 Chapter 2 Background 8 2.1 Neuromorphic chips 8 2.2 Fault model 10 2.3 Previous works 12 2.4 Statistical hypothesis testing 16 2.4.1 Introduction of hypothesis testing 16 2.4.2 Two-sample Hotelling’s T-Square Test 21 Chapter 3 Proposed Techniques 24 3.1 Overall flow 24 3.2 Fault detection with hypothesis testing 25 3.3 Fault dropping with contribution accumulation 27 3.4 Dynamic Test Compression (DTC) 30 3.5 Test pattern generation 33 3.6 Static Test Compression (STC) 34 Chapter 4 Experimental Results 37 4.1 Experimental setup 37 4.2 Test repetition determination 38 4.3 Test compression results 39 Chapter 5 Conclusion 43 References 44 Appendix A — Fault Detection Probability 50 A.1 Fault simulation time 50 A.2 Average fault detection probability 51 Appendix B — Example of Two-sample Hotelling’s T-Square Test 53 | - |
| dc.language.iso | en | - |
| dc.subject | 神經形態晶片 | zh_TW |
| dc.subject | 動態測試壓縮 | zh_TW |
| dc.subject | 脈衝神經網路 | zh_TW |
| dc.subject | 靜態測試壓縮 | zh_TW |
| dc.subject | 測試樣本生成 | zh_TW |
| dc.subject | Spiking Neural Network | en |
| dc.subject | dynamic test compression | en |
| dc.subject | static test compression | en |
| dc.subject | neuromorphic chip | en |
| dc.subject | test pattern generation | en |
| dc.title | 神經形態晶片的測試壓縮 | zh_TW |
| dc.title | Test Compression for Neuromorphic Chips | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 黃俊郎;呂學坤 | zh_TW |
| dc.contributor.oralexamcommittee | Jiun-Lang Huang;Shyue-Kung Lu | en |
| dc.subject.keyword | 神經形態晶片,脈衝神經網路,動態測試壓縮,靜態測試壓縮,測試樣本生成, | zh_TW |
| dc.subject.keyword | neuromorphic chip,Spiking Neural Network,dynamic test compression,static test compression,test pattern generation, | en |
| dc.relation.page | 57 | - |
| dc.identifier.doi | 10.6342/NTU202303828 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2023-08-10 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-111-2.pdf | 12.05 MB | Adobe PDF | 檢視/開啟 |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。