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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林宗賢 | zh_TW |
dc.contributor.advisor | Tsung-Hsien Lin | en |
dc.contributor.author | 張庭豪 | zh_TW |
dc.contributor.author | Ting-Hao Chang | en |
dc.date.accessioned | 2023-08-15T17:42:00Z | - |
dc.date.available | 2023-11-09 | - |
dc.date.copyright | 2023-08-15 | - |
dc.date.issued | 2023 | - |
dc.date.submitted | 2023-08-07 | - |
dc.identifier.citation | P. Larsson, "An offset-cancelled CMOS clock-recovery/demux with a half-rate linear phase detector for 2.5 Gb/s optical communication" IEEE ISSCC, pp. 74-75, Feb. 2001.
J. Zhu et al., "A 0.0021 mm2 1.82mW 2.2GHz PLL Using Time-based Integral Control in 65nm CMOS" IEEE ISSCC, pp. 338-340, Feb. 2016. W. C. Lindsey et al., "A survey of digital phase-locked loops" in Proceedings of the IEEE, vol. 69, no. 4, pp. 410-431, Apr. 1981. R. B. Staszewski et al., "Phase-Domain All-Digital Phase-Locked Loop" IEEE TCAS-II, vol. 52, no. 3, pp. 159-163, Mar. 2005. J. Tangudu et al., "Quantization noise improvement of time to digital converter (TDC) for ADPLL" IEEE ISCAS, pp. 1020-1023, May, 2009. J. Yu, et al., "A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 μm CMOS Technology" IEEE JSSC, vol. 45, no. 4, pp. 830-842, Apr. 2010. P. Madoglio, " Quantization effects in all-digital phase-locked loops" IEEE TCAS-II, vol. 43, no. 12, pp. 2776-2786, Dec. 2008. G. Marzin et al., "A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With −36 dB EVM at 5 mW Power" IEEE JSSC, pp. 2974-2988, Dec. 2012. C. M. Hsu et al., "A Low-Noise Wide-BW 3.6-GHz Digital ∆Σ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation" IEEE JSSC, vol. 43, no. 12, pp. 2776-2786, Dec 2008. D. Liao et al., " An 802.11 a/b/g/n digital fractional-N PLL with automatic TDC linearity calibration for spur cancellation" IEEE JSSC, vol. 52, no. 5, pp. 391-400, May 2017. S. Kim et al., "A 2 GHz synthesized fractional-N ADPLL with dual-referenced interpolating TDC" IEEE JSSC, vol. 43, no. 12, pp. 391-400, Feb 2016. C. R. Ho et al., "A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS" IEEE ISSCC, pp. 394-396, Feb. 2018. Z. Gao et al., " A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs" IEEE ISSCC, pp. 380-382, Feb. 2022. P. Chen et al., "A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS " IEEE JSSC, vol. 54, no. 11, pp. 3075-3085, Nov. 2019. Z. Gao et al., " A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs" IEEE ISSCC, pp. 380-382, Feb. 2022. S. M. Dartizio et al., " A 76.7 fs-lntegrated-Jitter and− 71.9 dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering" IEEE ISSCC, pp. 3-5, Feb. 2023. H. You et al., "A low-power high-speed sense-amplifier-based flip-flop in 55 nm MTCMOS" Electronics, May 2020. V. Kratyuk et al., "A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy" IEEE TCAS-II, vol. 54, no. 3, pp. 247-251, Mar. 2007. M. Lee et al., "A 0.0043-mm 2 0.3–1.2-V frequency-scalable synthesized fractional-N digital PLL with a speculative dual-referenced interpolating TDC" IEEE JSSC, vol. 56, no. 1, pp. 99-108, Jan. 2019. K. Kwon et al., "Open-Source Fully-Synthesizable ADPLL for a Bluetooth Low-Energy Transmitter in 12nm FinFET Technology" IEEE RFIC, pp. 155-158, June 2022. S. J. Kim et al., "A 0.6 V 1.17 ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology" IEEE ISSCC, pp. 1-3, Feb. 2015. N. Pavlovic et al., "A 5.3 GHz digital-to-time-converter-based fractional-N all-digital PLL" IEEE ISSCC, pp. 394-396, Feb. 2018. B. Razavi, "A study of injection locking and pulling in oscillators" IEEE JSSC, vol. 39, no. 9, pp. 1415-1424, Sep. 2004. R. Farjad-Rad et al., " A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips" IEEE JSSC, vol. 37, no. 12, pp. 1804-1812, Dec. 2002. Z. Matthew et al., " A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping" IEEE JSSC, vol. 44, no. 4, pp. 1089-1098, Apr. 2009. | - |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/88766 | - |
dc.description.abstract | 本論文實現一個基於小數型全數位鎖相迴路兩點調製架構,在所提出的兩點調製器中,利用前饋消除技術消除兩信號注入點間的路徑延遲擴展。此架構採用計數器為基礎的數位鎖相迴路以達到極短的鎖定時間,時間數位轉換器運用亞時間數位轉換器對應環形振盪器多相位輸出降低單位數位轉換器所需偵測範圍,時間數位轉換器採用雙內插法克服時間數位轉換器因跳頻造成的增益誤差,並仍保有良好的線性度。以數位時間轉換器在回授路徑添加額外的噪聲抖動,隨機化時間數位轉化器的輸入信號,以降低鎖相迴路輸出之小數突波。
此鎖相迴路系統操作於1.2V,共花費6.71 mA電流,輸入參考時脈信號頻率為40 MHz,可輸出信號頻率為23.5至24.5 GHz,採用TSMC 90奈米製程設計,在2.4000390625 GHz下,所量測到的小數突波為-39 dBc。在2.4 GHz下,所量測的相位雜訊於1 MHz頻率偏移下為-99 dBc/Hz,由1 kHz積分到100 MHz的均方根抖動為2.24 ps,FoMJitter為-223dB。 | zh_TW |
dc.description.abstract | The thesis implement a Two-Point Modulation (TPM) architecture based on a fractional-N all digital phase-locked loop. In the proposed two-point modulator, the feedforward cancellation technique is used to eliminate the path delay spread between two signal injection points. This architecture uses a counter-based digital phase-locked loop to achieve extremely short lock times. The Time-to-Digital Converter (TDC) utilizes a set of sub-TDCs that correspond to the multi-phase output of the ring oscillator. This approach helps in reducing the detection range required for each individual sub-TDC. The converter adopts double interpolation method to overcome the TDC conversion gain error caused by frequency hopping, and still maintains good linearity. Noise dithering at the feedback path by a Digital-to-Time Converter (DTC) randomizes the TDC input signal pattern so that the fractional spur of the PLL output is reduced.
The TPM architecture is implemented in the design a 2.35-2.45 GHz ADPLL. Fabricated in the TSMC 90-nm CMOS technology, the whole system dissipates 6.71 mA from a 1.2 V supply and the active area is 0.108 mm2. At 2.4000390625 GHz, the fractional spur is -39 dBc. At 2.4 GHz, the phase noise measured at 1 MHz offset is -99 dBc/Hz. RMS jitter integrated from 1 kHz to 100 MHz is 2.24 ps and figure-of-merit (FOM) is -223 dB. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-08-15T17:42:00Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2023-08-15T17:42:00Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | 審定書 i
摘要 v Abstract vii List of Figures xi List of Tables xv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Overview 3 Chapter 2 Introduction to All-Digital PLL & Two Point Modulation Technology 5 2.1 Basics of All-Digital-Phase-Locked Loops 5 2.2 Quantization Noise Analysis of Fractional-N ADPLL 7 2.2.1 TDC Quantization Noise 8 2.2.2 DCO Quantization Noise 9 2.3 Frequency Shift Keying (FSK) Modulation using Two Point Modulation (TPM) Technology 10 2.3.1 DCO Gain Variation for TPM architecture 11 2.3.2 Adaptive Gain Compensation of DCO 12 2.3.3 Path Delay Spread for TPM architecture 13 2.3.4 Proposed Delay Spread compensation to ADPLL 14 Chapter 3 TDC and DTC Linearization Technology 17 3.1 TDC Conversion Gain Variation during Frequency Hopping 17 3.2 Dual-Referenced Interpolating TDC 19 3.3 Quadruple-Referenced Interpolating TDC 23 3.4 Noise Dithering using Inverse DTC 26 3.4.1 DTC Based on Time-Mode Arithmetic Units 28 3.4.2 Inverse DTC Based on a Pulse Generator 29 3.4.3 Immunity to Channel-Length Modulation 30 Chapter 4 Implementation of a 2.4 GHz Fractional-N All-Digital PLL 33 4.1 Analog Design 34 4.1.1 Digital-Controlled Oscillator 34 4.1.2 Synchronous Counter and Sampling Circuit 35 4.1.3 Time-to-Digital Converter 36 4.1.4 Sense-Amplifier-Based Flip-Flop 39 4.1.5 Digital-to-Time Converter 40 4.2 RTL Design 42 4.2.1 Digital Loop Filter 42 4.2.2 Frequency Hopping Control Logic 44 4.2.3 Fast Locking Function 45 4.2.4 Arbiter 47 4.2.5 Calibration for DTC 48 4.2.6 Other Block 48 Chapter 5 Measurement Results 51 5.1 Measurement Setup 51 5.2 Chip Pin Configuration and Chip Photo 52 5.3 Measurement Results 53 5.3.1 Spectrum & Phase Noise for Integer-N channel 53 5.3.2 Spectrum & Phase Noise of a Near-Integer Fractional-N Channel 55 5.3.3 Loop-Bandwidth Drifts vs. DCO Nonlinearity 59 5.3.4 Frequency Hopping Measurement with TPM Architecture 60 5.3.5 BFSK Modulation Measurement with TPM Architecture 61 5.4 Summary 62 Chapter 6 Conclusions and Future Works 65 6.1 Conclusions 65 6.2 Directions for Improvement of this Chip 66 6.2.1 Loop-Bandwidth Tuning Capability 66 6.2.2 Calibration Loop Optimization 66 6.2.3 Enhancement of DCO Linearity 67 6.2.4 Other 67 6.3 Directions for Improvement of this Chip 68 6.2.1 Motivation 68 6.2.2 DTC-Assisted ADPLL 68 6.2.3 Rewritten of DTC Predicted Delay 69 6.2.4 Time-Register using Time-Mode Arithmetic Units 71 6.2.5 Proposed Time-Registers-Based ADPLL 72 6.2.6 Issues Still to be Resolved 73 6.2.7 Possible Solutions 74 References 77 | - |
dc.language.iso | en | - |
dc.title | 一個具有時間數位轉換器和數位延遲轉換器線性化技術應用於頻率鍵移調變之小數型全數位鎖相迴路 | zh_TW |
dc.title | A Fractional-N All-Digital Phase-Locked Loop using TDC and DTC Linearization Technology for FSK Application | en |
dc.type | Thesis | - |
dc.date.schoolyear | 111-2 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 蔡宗亨;呂良鴻 | zh_TW |
dc.contributor.oralexamcommittee | Tsung-Heng Tsai;Liang-Hung Lu | en |
dc.subject.keyword | 全數位鎖相迴路,兩點調製,時間數位轉換器,數位時間轉換器,雙插值法, | zh_TW |
dc.subject.keyword | All-Digital Phase-Locked Loop,Two-Point Modulation,Time-to-Digital Converter,Digital-to-Time Converter,Double Interpolation, | en |
dc.relation.page | 79 | - |
dc.identifier.doi | 10.6342/NTU202303265 | - |
dc.rights.note | 同意授權(全球公開) | - |
dc.date.accepted | 2023-08-09 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
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