使用半旋轉頻率偵測與增強抖動容忍技術之鮑率時脈資料還原電路

Abstract

這篇論文的主題主要分為兩個部分，第一部分實現了一個 12.93-16 Gb/s 無參考頻率與時脈資料還原電路，該電路具有一階決策反饋均衡器 (DFE)。通過使用半旋轉頻率檢測算法，設計了一種鮑率頻率檢測器。該頻率檢測器重複使用了相位檢測器和一階決策反饋均衡器的硬體。此電路採用 40 奈米 CMOS 技術製造。面積與功耗分別為 0.117mm² 和 40.6mW，在速率為 16Gb/s 計算得到的功耗效率為 2.54pJ/bit。 第二部分實現了一個具有一階決策反饋均衡器的 20Gb/s 數位時脈資料還原電路。為了擴大時鐘的時序區域，我們提出了一個前景校準電路，用於校準比較器的閾值電壓，這能夠增強抖動容忍度（JTOL）。這個時脈資料還原電路（CDR）使用 40 奈米 CMOS 技術製造，其有效面積為 0.103 mm²。總功率為47.6mW，計算得出的功耗效率在 20Gb/s 時為 2.38 pJ/bit。測得的高頻 JTOL 大於 0.2UIᴘᴘ。這個前景校準電路的測得收斂時間小於 12.7μs。

This thesis consists of two parts. The first part presents a 12.93-16Gb/s reference-less and baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE). By using the semirotational frequency detection algorithm, a baud-rate frequency detector (FD) is presented. This FD reuses the hardware of the pattern-based phase detector and the one-tap DFE. This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.117 mm² . The total power is 40.6mW and the calculated power efficiency is 2.54 pJ/b at 16Gbps. The second part presents a 20Gb/s baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE). To widen the timing region of the clock, a foreground calibration circuit is presented to calibrate the threshold voltage of the comparator. It enhances the jitter tolerance (JTOL). This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.103 mm² . The total power is 47.6mW and the calculated power efficiency is 2.38pJ/b at 20Gb/s. The measured high-frequency JTOL is larger than 0.2UIᴘᴘ. The measured settling time of this foreground calibration circuit is less than 12.7μs.