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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉致為 | zh_TW |
| dc.contributor.advisor | Chee Wee Liu | en |
| dc.contributor.author | 闕世杰 | zh_TW |
| dc.contributor.author | Shee-Jier Chueh | en |
| dc.date.accessioned | 2023-08-09T16:14:55Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-08-09 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-07-24 | - |
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Feng, et al., Journal of the Electrochemical Society 144.3, 1997, L37. [32] D. D. Cannon et al., “Tensile strained epitaxial Ge films on Si(100) substrates with potential application in L-band telecommunications,”Appl. Phys. Lett., vol. 84, no. 6, pp. 906–908, Feb. 2004, doi:10.1063/1.1645677. [33] S. Sun, Y. Sun, Z. Liu, D.-I. Lee, S. Peterson, and P. Pianetta, “Surface termination and roughness of Ge(100) cleaned by HF and HCl solutions,”Appl. Phys. Lett., vol. 88, no. 2, Jan. 2006, Art. no. 021903, doi:10.1063/1.2162699. [34] T.-E. Lee, K. Kato, M. Ke, M. Takenaka, and S. Takagi, “Improvement of SiGe MOS interface properties with a wide range of Ge contents by using TiN/Y2O3 gate stacks with TMA nassivation,”in Proc. Symp. VLSI Technol., Jun. 2019, pp. T100–T101, doi:10.23919/VLSIT.2019.8776523. [35] T.-E. Lee, M. Ke, K. Toprasertpong, M. Takenaka, and S. Takagi, “Reduction of MOS interface defects in TiN/Y2O3/Si0.78Ge0.22 structures by trimethylaluminum treatment,”IEEE Trans. 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Tsai et al., "Highly Stacked 8 Ge0.9Sn0.1 Nanosheet pFETs with Ultrathin Bodies (~3nm) and Thick Bodies (~30nm) Featuring the Respective Record ION/IOFF of 1.4x107 and Record ION of 92μA at Vov=VDS= -0.5V by CVD Epitaxy and Dry Etching," 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2021, pp. 26.4.1-26.4.4, doi: 10.1109/IEDM19574.2021.9720660. [47] C. -T. Tu, Y. -C. Liu, Y. -R. Chen, B. -W. Huang, C. -Y. Cheng and C. W. Liu, "Nanosheet Extensions and Beyond," 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), HsinChu, Taiwan, 2023, pp. 1-1, doi: 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134258. [48] C. -T. Tu et al., "First Demonstration of Monolithic 3D Self-aligned GeSi Channel and Common Gate Complementary FETs by CVD Epitaxy Using Multiple P/N Junction Isolation," 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 20.3.1-20.3.4, doi: 10.1109/IEDM45625.2022.10019532. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/88258 | - |
| dc.description.abstract | 自1940年電晶體的發明以來，技術的進步已將其尺寸推向極限，摩爾定律恰好描述了每兩年電晶體數量翻倍的情況，至今仍然適用。MOSFET由於其卓越的設計，已成為邏輯IC的首選。而FinFET取代了平面MOSFET，而GAAFET將以其較佳的閘極控制力接續FinFET，因其在縮小寬度和實現高寬比方面具有優勢。2022年，GAAFET在量產中正式取代了FinFET。望後數十年的努力目標，包 含於鍺(Ge)的材料和使用GAA元件結構。
我們通過化學氣相沉積磊晶和高選擇性的蝕刻來製作高通道層數堆疊的鍺矽(GeSi)電晶體。GeSi是一種高遷移率通道材料，被視為下一個世代的通道材料。磊晶層被精心設計以創建高度堆疊的元件結構。TEM、HRXRD、RSM和SIMS等證實了磊晶層的成功生長和GeSi通道中的應變(strain)。製程流程包括化學氣相沉積磊晶、黃光製程、乾蝕刻(fin formation)及濕蝕刻(channel release)。濕蝕刻中，H2O2用於去除鍺犧牲層(sacrificial layers)，而NH4OH則去除了Ge緩衝層(buffer)下的不需要的SOI (Silicon On Insulator)層，並且討論了兩者的濕蝕刻機制。我們成功展示了使用Ge0.95Si0.05和Ge0.75Si0.25通道層製作奈米片和奈米線電晶體的挑戰和製造流程，且無需進行源極-汲極再生長(S/D regrow)。 Lg =80nm的8通道堆疊Ge0.75Si0.25奈米片在VOV = VDS = 0.5V時，ION =36μA（390μA/μm 對通道所占面積標準化），次臨界擺幅SS=121mV/dec；Lg =70nm的7通道堆疊Ge0.95Si0.05奈米線在VOV = VDS = 0.5V時， ION =128μA（為5800μA/μm對通道所占面積標準化），次臨界擺幅SS=112mV/dec。我們討論了寄生通道的存在對於元件I-V特性的影響。另外還探討了微橋效應(microbridge effect)，顯示了微橋結構帶來了增強的伸應變(tensile strain)和更好電子遷移率(electron mobility)。總體而言，製造的鍺矽奈米片和奈米線展示了好的I-V特性和應用於先進製程的潛力。 未來工作總結為三個方向：精進製程技術、縮小電晶體尺寸以提高元件性能，以及製作下一代電晶體結構:互補式場效電晶體(CFET)。 | zh_TW |
| dc.description.abstract | Since the invention of the transistor, technological advancements have pushed its size to the limits. The FinFET replaced planar MOSFETs, and GAAFETs are set to take over with superior gate controllability and electrostatic characteristics. GAAFETs offer advantages in scaling down width and achieving high aspect ratios. In 2022, GAAFETs replaced FinFETs in mass production. Future innovations include Ge-based materials and the adoption of GAA structure in device architecture.
We explore the fabrication of highly stacked GeSi channels using epitaxial structures and selective etching. GeSi, a high mobility channel material, is investigated as an alternative to enhance CMOS performance. The process flow involves epitaxy growth, lithography, fin formation, and channel release. Wet etching with H2O2 is used to selectively remove sacrificial layers, while NH4OH eliminates unwanted layers beneath the Ge buffer. Discussion of the wet etching mechanism and the challenges and successful fabrication of nanosheet and nanowire devices using Ge0.95Si0.05 and Ge0.75Si0.25 channel layers are presented. The epitaxy layers are carefully designed to create a highly stacked device structure. Various techniques, such as TEM, HRXRD, RSM, and SIMS, confirm the successful growth of epitaxy layers and strain in the GeSi channels. The fabrication process includes steps such as thinning the SOI substrate, growing a Ge buffer layer, deposition of sacrificial and channel layers, gate stack formation, and S/D contact formation. The process is completed with the sputter deposition of S/D contacts using Pt. These devices hold promise for high-performance semiconductor devices and integrated circuits. The electrical properties of the nanosheets and nanowires are comprehensively investigated, the 8 stacked Ge0.75Si0.25 nanosheets, each with an Lg of 80nm, exhibit an ION of 36μA per stack (390μA/μm per channel footprint) at VOV and VDS of 0.5V, with a SS of 121mV/dec and the 7 stacked Ge0.95Si0.05 nanowires, each with an Lg of 70nm, exhibit an ION of 128μA per stack (5800μA/μm per channel footprint) at VOV = VDS = 0.5V, with a SS of 112mV/dec. The effect of parasitic channels is discussed, which affects the I-V characteristics in the IOFF region of the devices. The microbridge effect is also explored, showing enhanced tensile strain and electron mobility. In short, the fabricated GeSi nanosheets and nanowires demonstrate desirable electrical characteristics and potential for advanced transistor applications. In the end, future work is summarized in three directions: improve the processing technique, scale down certain dimensions to improve device performance, and build the next-generation device CFET, integrating the nanosheet or nanowire structure we discuss in this article. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-08-09T16:14:55Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-08-09T16:14:55Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Table of Content
口試委員審定書 i 誌謝 ii IEDMS Best Student Paper Award iii Roger A. Haken Best Student Paper Award iv NTU Transistors Highlighted by VLSI and Nature Electronics in 2021 v VLSI-TSA Best Student Award vi Publication List (相關論文發表) vii 摘要 ix Abstract xi Table of Content xiii List of Figures xvi List of Tables xix Chapter 1 Introduction 1 1.1 Research Background and Purpose 1 1.2 Thesis Structure Organization 7 Chapter 2 Channel Release for Highly Stacked GeSi Nanosheets and Nanowires 9 2.1 Introduction 9 2.2 Process Flow of Stacked Channels 12 2.3 Channel Release for GeSi Channels 13 2.3.1 H2O2 and NH4OH Wet Etching Mechanism 13 2.3.2 Discussion of Ge0.95Si0.05 and Ge0.75Si0.25 16 2.4 Summary 17 Chapter 3 Fabrication of Highly Stacked GeSi Nanosheets and Nanowires 19 3.1 Introduction 19 3.2 Epitaxy Layers Design 20 3.3 Device Fabrication 23 3.4 Summary 29 Chapter 4 Electrical Properties, Device Images, Strain Simulation of GeSi Nanosheets and Nanowires 31 4.1 Introduction 31 4.2 Device Images and Electrical Properties of Nanosheets and Nanowires 32 4.3 Parasitic Channel 36 4.4 Strain Simulation 39 4.5 Summary 42 Chapter 5 Summary and Future Work 44 5.1 Summary 44 5.2 Future Work 44 Reference 46 | - |
| dc.language.iso | en | - |
| dc.subject | n型閘極環繞式電晶體 | zh_TW |
| dc.subject | 奈米片 | zh_TW |
| dc.subject | 通道釋放 | zh_TW |
| dc.subject | 鍺矽 | zh_TW |
| dc.subject | 應變模擬 | zh_TW |
| dc.subject | 奈米線 | zh_TW |
| dc.subject | Nanosheet | en |
| dc.subject | GeSi | en |
| dc.subject | Channel Release | en |
| dc.subject | Nanowire | en |
| dc.subject | nGAAFET | en |
| dc.subject | Strain Simulation | en |
| dc.title | 高層數堆疊鍺矽通道奈米片及奈米線電晶體之製程整合 | zh_TW |
| dc.title | Process Integration of Highly Stacked GeSi Nanosheets and Nanowires FETs | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 林中一;林楚軒;李敏鴻;廖洺漢 | zh_TW |
| dc.contributor.oralexamcommittee | Chung-Yi Lin;Chu-Hsuan Lin;Min-Hung Lee;Ming-Han Liao | en |
| dc.subject.keyword | n型閘極環繞式電晶體,奈米片,奈米線,鍺矽,通道釋放,應變模擬, | zh_TW |
| dc.subject.keyword | nGAAFET,Nanosheet,Nanowire,GeSi,Channel Release,Strain Simulation, | en |
| dc.relation.page | 54 | - |
| dc.identifier.doi | 10.6342/NTU202301581 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2023-07-25 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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