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標題: | 應用於第三代高頻寬記憶體在晶圓級系統集成內矽中介層之訊號與電源完整度優化 Optimized Signal and Power Integrity of Silicon Interposer for HBM3 in CoWoS |
作者: | 林桂如 Kuei-Ju Lin |
指導教授: | 吳瑞北 Ruey-Beei Wu |
關鍵字: | 串擾,不匹配傳輸,眼圖優化,交錯式布線,訊號完整度,電源完整度,晶圓級系統集成, Crosstalk,Mismatched Transmission,Eye Diagram Optimization,Interleaved Routing,Signal Integrity,Power Integrity,CoWoS, |
出版年 : | 2023 |
學位: | 碩士 |
摘要: | 在第二代增強版高頻記憶體的基礎上,對速率提高至少一倍的第三代高頻記憶體,本文就其晶圓級系統集成中連接記憶體和系統單晶片的矽中介層,進行訊號及電源完整度的分析與優化設計。
在訊號完整度部份,針對速度提升後對串擾敏感度提升問題,本文提出新的錯綜佈線方式,使電容電感耦合係數獲得至少5倍改善。同時也利用快速預測不匹配傳輸系統眼高優化之演算,對傳輸線特性阻抗進行優化改善,使速率提升一倍後,訊號不受串擾嚴重影響,在上升時間為15ps的6.4Gbps速度下,從11%改善4.6倍獲得51%良好的眼圖睜開度。 在電源完整度部份,考慮電源線對訊號傳輸之電感耦合影響,通過調整電源線與地線的佈線方式,降低電源與傳輸線間的電感值達原本的0.1倍,通過建立記憶體至系統單晶片間的等效電路,並考慮各訊號切換時的晶片噪音進行評估,最終使輸出眼睛睜開度從整體35%增加至約48%,距原本串擾傳輸線的眼睛睜開度降低程度減少25%。 Based on the second-generation enhanced high-frequency memory (HBM2E), the evolving third-generation high-frequency memory (HBM3) has higher speed at least doubled. Regarding to its Chip on Wafer on Substrate (CoWoS) packaging structure, this thesis addressed the analysis and improved design on the signal and power integrity for the signal transition in silicon interposer layers connecting memory and SoC. For the signal integrity, a new intricate wiring scheme is proposed to deal with the increased crosstalk susceptibility due to the higher operating speed so that the capacitive and inductive coupling coefficients can be improved by at least 5 times. In addition, using the fast algorithm for the eye height optimization of mismatched transmission system, the characteristic impedance of the transmission line is optimized. At a doubled speed of 6.4Gbps with rise time of 15ps, the signal is not seriously affected by crosstalk and the eye-opening is improved by 4.6 times, from 11% to 51%. For the power integrity, this thesis considered the influence of the inductive coupling of the power line on the signal transmission. The wiring scheme in the power and the ground lines is adjusted to reduce the inductance between the power supply and the transmission line by ten times. By establishing an equivalent circuit between the memory and the system chip and considering the on-chip noise when each signal is switched for evaluation, the output eye-opening is increased from the overall 35% to about 48%, and the influence on eye-opening due to the crosstalk from the original coupled transmission lines is reduced by 25%. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87838 |
DOI: | 10.6342/NTU202300693 |
全文授權: | 同意授權(限校園內公開) |
顯示於系所單位: | 電信工程學研究所 |
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