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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳安宇 | zh_TW |
| dc.contributor.advisor | An-Yeu Wu | en |
| dc.contributor.author | 王則勛 | zh_TW |
| dc.contributor.author | Tse-Hsun Wang | en |
| dc.date.accessioned | 2023-06-20T16:06:21Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-06-20 | - |
| dc.date.issued | 2022 | - |
| dc.date.submitted | 2022-10-28 | - |
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IRE 40, 9 (Sep. 1952), 1098–1101. [21] Song Han, Huizi Mao, and William J. Dally. 2015. Deep compression: Compressing deep neural network with pruning, trained quantization, and Huffman coding. CoRR abs/1510.00149. [22] Y. Choi, M. El-Khamy and J. Lee, "Universal Deep Neural Network Compression," in IEEE Journal of Selected Topics in Signal Processing, vol. 14, no. 4, pp. 715-726, May 2020, doi: 10.1109/JSTSP.2020.2975903. [23] Andrew G. Howard, Menglong Zhu, Bo Chen, Dmitry Kalenichenko, Weijun Wang, Tobias Weyand, Marco Andreetto, and Hartwig Adam. Mobilenets: Efficient convolutional neural networks for mobile vision applications. CoRR, abs/1704.04861, 2017 [24] M. Rhu, M. O'Connor, N. Chatterjee, J. Pool, Y. Kwon, and S. W. Keckler, "Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks," 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018, pp. 78-91, doi: 10.1109/HPCA.2018.00017. [25] Y. -H. Chen, T. -J. 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IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021, pp. 1-4. [29] G. Retsinas, A. Elafrou, G. Goumas, and P. Maragos, "Weight Pruning via Adaptive Sparsity Loss," arXiv e-prints, p. arXiv:2006.02768. [Online]. Available: https://ui.adsabs.harvard. edu/abs/ 2020arXiv2006 02768R [30] (2020 ISLPED) GRLC Grid-based Run-length Compression for Energy-efficient CNN Accelerator [31] Gil Shomron, Freddy Gabbay, Samer Kurzum, and Uri Weiser. Post-training sparsity-aware quantization. arXiv preprint arXiv:2105.11010, 2021. [32] L. Cavigelli, G. Rutishauser, and L. Benini, "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 9, no. 4, pp. 723-734, Dec. 2019 | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87567 | - |
| dc.description.abstract | 隨著現在深度學習的蓬勃發展,深度學習已經是解決各種問題的重要方法。然而,深度學習的運算量非常龐大,以往只能在伺服器上做運算。然而近年來,大資料時代讓資料量呈現指數性的成長。如果我們只於伺服器上做深度學習運算,我們必須面對傳輸資料時間過長和資料隱私的問題。為了解決上述問題,大多研究都指向把深度學習實做在邊緣端,利用深度學習加速器提高運算效能。邊緣端的深度學習加速器仍然需要克服許多困難,最重要的是其高能耗的特性。其能量消耗來自兩個原因,一個是運算上的消耗,另一個是在資料傳輸上的消耗,而後者也是大家往往所忽略的。在深度學習加速器上,每當進行一層運算時,我們時常需要先把激活值的結果從動態隨機存取記憶體 (DRAM) 中取出,運算後再將結果放進DRAM中,因此造成高能量消耗。針對這個問題,本文利用資料壓縮的方式,將輸出激活值壓縮,以減少能量的消耗。本文會利用激活值有很高稀疏性的特性,使用零資料壓縮 (Zero-value Compression, ZVC)技術,此外我們還會搭配塊狀壓縮 (Block Compression, BC) 和繞過機制 (Bypass Mechanism),讓壓縮率來到2.39倍。另外,我們也提出K有損壓縮 (K-lossy Compression),在只降低0.4%準確率的情況下,讓壓縮率來到3.73倍。最後,我們會結合上述提及的演算法優化技術,提出一可調整架構(Scalable architecture)的資料壓縮/解壓縮引擎,相較於代表作,吞吐量提高19%,並只有增加8%的面積。最後用DRAMSim2來驗證此引擎能降低56%在DRAM資料傳輸上的消耗。 | zh_TW |
| dc.description.abstract | As the development of deep learning (DL) has become more and more popular, DL has become an important solution to different kinds of problems. However, DL requires a large amount of computation, which can be computed on the cloud. In recent years, the number of data increases exponentially. Thus, cloud-based DL systems face the challenge of large data transmissions and data privacy leakages. To address these issues, most of the research aims to move the inferencing of the DL system to edge devices. The DL accelerators are developed to enhance the computational efficiency of the inferencing process. However, the DLA consumes a lot of energy. There are two aspects to reducing energy consumption: computation and data transmission. We will focus on reducing the energy consumption of the data transmission as it is the bottleneck in the current DLA. When computing a layer in the DLA, the activations are fetched from the DRAM. After computations in DLA, the output activations are stored back in DRAM. The data transmission between the DLA and DRAM causes high energy consumption. In this thesis, we use activation compression (AC) techniques to reduce the transmission between the DLA and DRAM and thus reduce the overall energy consumption. We exploit the high sparsity of activations generated from the ReLU function. The zero-value compression (ZVC) is combined with the block compression and the bypass mechanism. It can achieve a ×2.39 compression ratio. We also propose two K-lossy compression techniques, that is mixed-K lossy compression and K-lossy aware training. With 0.4% accuracy drops, we can achieve a ×3.73 compression ratio. Finally, combining the above algorithms, we propose a scalable architecture and implement it with hardware. The proposed scalable architecture can outperform the state-of-the-art by increasing by 19% throughput with 8% hardware overhead. The overall system’s energy consumption is also verified with DRAMSim2, showing that our method reduces read energy and write energy by 56%. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-06-20T16:06:21Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-06-20T16:06:21Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝 vii
摘要 ix ABSTRACT xi CONTENTS xiii LIST OF FIG.URES xvi LIST OF TABLES xx Chapter 1 Introduction 1 1.1 Background 1 1.1.1 The Background of Deep learning 1 1.1.2 Deep Learning from Cloud to Edge 3 1.1.3 Deep Learning Accelerator (DLA) 5 1.2 Motivation and Main Contributions 6 1.2.1 The architecture of DLA 6 1.2.2 The bottleneck of DLA 7 1.2.3 Thesis Target 8 1.3 Thesis Organization 9 Chapter 2 Review of Activation Compression 10 2.1 Related Works of Activation Compression 10 2.1.1 Entropy Coding 10 2.1.2 Zero-value compression (ZVC) 11 2.1.3 Zero Run-length Coding (Z-RLC) 13 2.1.4 Lane Compression 16 2.2 Challenges of the Prior Works 18 2.3 Summary 19 Chapter 3 Algorithm of Compression 20 3.1 Proposed Bit-level ZVC 20 3.1.1 Block Compression 20 3.1.2 Bypass Mechanism 23 3.2 K-Lossy Compression 26 3.2.1 Analysis of K-Lossy 26 3.2.2 Mixed K-lossy Compression 30 3.3 K-lossy-aware Training 35 3.3.1 Add K-lossy Noise 35 3.3.2 Simulation Result 36 3.4 Budget-aware Compression 39 3.4.1 Problem Formulation 39 3.4.2 Budget-aware Compression 42 3.4.3 Simulation Result 44 3.5 Summary 45 Chapter 4 Hardware IP and System Analysis 46 4.1 Hardware of Compressor 46 4.1.1 The Architecture of Compressor 46 4.1.2 Basic Function 48 4.1.3 ZVC and Block Compression 51 4.1.4 Proposed Scalable Bit-level Non-Zero Values Concatenation 53 4.1.5 Output Wrapper 55 4.2 Hardware of Decompressor 57 4.2.1 The Architecture of Decompressor 57 4.2.2 Input Unpacker 59 4.2.3 The Decompression Method 60 4.2.4 Proposed Scalable Bit-level Decompressor 61 4.3 Performance Results 63 4.3.1 Performance Analysis of Different Sizes of Sub-block 63 4.3.2 Performance Analysis of Related Work 64 4.4 System Analysis 65 4.4.1 Power analysis 65 4.4.2 DRAMSim2 66 4.4.3 Simulation Results 68 4.5 Summary 70 Chapter 5 Main Contribution and Future Directions 71 5.1 Main Contribution 71 5.2 Future Directions 72 REFERENCE 73 | - |
| dc.language.iso | en | - |
| dc.subject | 可調整架構 | zh_TW |
| dc.subject | 有損壓縮 | zh_TW |
| dc.subject | 塊狀壓縮 | zh_TW |
| dc.subject | 激活值壓縮 | zh_TW |
| dc.subject | 零資料壓縮 | zh_TW |
| dc.subject | 繞過機制 | zh_TW |
| dc.subject | Zero-value compression | en |
| dc.subject | Bypass Mechanism | en |
| dc.subject | K-lossy | en |
| dc.subject | Block Compression | en |
| dc.subject | Activation compression | en |
| dc.subject | scalable architecture | en |
| dc.title | 基於稀疏性之低記憶體使用量激活值壓縮引擎設計 | zh_TW |
| dc.title | Sparsity-based Activation Compression Engine Design for Low-memory Access in DLA | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 盧奕璋;沈中安 | zh_TW |
| dc.contributor.oralexamcommittee | Yi-Chang Lu;Chung-An Shen | en |
| dc.subject.keyword | 激活值壓縮,零資料壓縮,塊狀壓縮,繞過機制,有損壓縮,可調整架構, | zh_TW |
| dc.subject.keyword | Activation compression,Zero-value compression,Block Compression,Bypass Mechanism,K-lossy,scalable architecture, | en |
| dc.relation.page | 76 | - |
| dc.identifier.doi | 10.6342/NTU202210009 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2022-10-31 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位: | 電子工程學研究所 | |
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