請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87511完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文 | zh_TW |
| dc.contributor.advisor | Yao-Wen Chang | en |
| dc.contributor.author | 李崇嘉 | zh_TW |
| dc.contributor.author | Chung-Chia Lee | en |
| dc.date.accessioned | 2023-06-14T16:04:15Z | - |
| dc.date.available | 2025-02-02 | - |
| dc.date.copyright | 2023-06-14 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-02-04 | - |
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Graduate Institute of Electronics Engineering, National Taiwan University, 2014. [16] Y.-K. Ho and Y.-W. Chang, “Multiple chip planning for chip-interposer codesign,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1–6, Austin, TX, USA, June 2013. [17] J.-M. Lin and Y.-W. Chang, “TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 842–847, New Orleans, LA, USA, June 2002. [18] S. Jangam, A. A. Bajwa, K. K. Thankkappan, P. Kittur, and S. S. Iyer, “Electrical characterization of high performance fine pitch interconnects in siliconinterconnect fabric,” in Proceedings of IEEE Electronic Components and Technology Conference, pp. 1283–1288, San Diego, CA, USA, May 2018. [19] J.-M. Lin and Y.-W. Chang, “TCG: A transitive closure graph-based representation for non-slicing floorplans,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 764–769, Las Vegas, NV, USA, June 2001. [20] W.-H. Liu, M.-S. Chang, and T.-C. Wang, “Floorplanning and signal assignment for silicon interposer-based 3D ICs,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1–6, San Francisco, CA, USA, June 2014. [21] T. Ma and E. F. Y. Young, “TCG-based multi-bend bus driven floorplanning,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 192-197, Seoul, Korea, March 2008. [22] R. Mahajan, Z. Qian, R. S. Viswanath, S. Srinivasan, K. Ayg¨un, W.-L. Jen, S. Sharan, and A. Dhall, “Embedded multidie interconnect bridge—a localized, high-density multichip packaging interconnect,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 10, pp. 1952–1962, 2019. [23] R. Mahajan and S. Sane, “Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same,” U.S. Patent 8 064 224, November 22, 2011. [24] R. Mahajan, R. Sankman, N. Patel, D.-W. Kim, K. Aygun, Z. Qian, Y. Mekonnen, I. Salama, S. Sharan, D. Iyengar, and D. Mallik, “Embedded multi-die interconnect bridge (EMIB) – a high density, high bandwidth packaging interconnect,” in Proceedings of IEEE Electronic Components and Technology Conference, pp. 557–565, Las Vegas, NV, USA, May 2016. [25] E. Nasiri, J. Shaikh, A. Hahn Pereira, and V. Betz, “Multiple dice working as one: CAD flows and routing architectures for silicon interposer FPGAs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1821–1834, 2016. [26] S. Osmolovskyi, J. Knechtel, I. L. Markov, and J. Lienig, “Optimal die placement for interposer-based 3D ICs,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 513–520, Jeju Island, Korea, January 2018. [27] D. P. Seemuth, A. Davoodi, and K. Morrow, “Flexible interconnect in 2.5D ICs to minimize the interposer’s metal layers,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 372–377, Chiba, Tokyo, January 2017. [28] R. Starkston, D. Malik, J. S. Guzek, C.-P. Chiu, D. Kulkarni, and R. V. Mahajan, “Localized high density substrate routing,” U.S. Patent 9 136 236, September 15, 2015. [29] D. Steinkraus, I. Buck, and P. Simard, “Using GPUs for machine learning algorithms,” in Proceedings of International Conference on Document Analysis and Recognition, pp. 1115–1120, Seoul, South Korea, August 2005. [30] M. Sunohara, T. Tokunaga, T. Kurihara, and M. Higashi, “Silicon interposer with TSVs (through silicon vias) and fine multilayer wiring,” in Proceedings of IEEE Electronic Components and Technology Conference, pp. 847–852, Lake Buena Vista, FL, USA, May 2008. [31] H.-F. Tsao, P.-Y. Chou, S.-L. Huang, Y.-W. Chang, M. P.-H. Lin, D.-P. Chen, and D. Liu, “A corner stitching compliant B*-tree representation and its applications to analog placement,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 507–511, San Jose, CA, USA, November 2011. [32] I.-P. Wu, QB-Trees: Towards an Optimal Topological Representation and its Applications to Analog Layout Designs. Graduate Institute of Electronics Engineering, National Taiwan University, 2016. [33] I.-P. Wu, H.-C. Ou, and Y.-W. Chang, “QB-trees: Towards an optimal topological representation and its applications to analog layout designs,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1–6, Austin, TX, USA, June 2016. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87511 | - |
| dc.description.abstract | 現今異質整合 (heterogeneous integration) 除了將不同功能及製程的晶片做整合以外，也需要滿足晶片間的高密度連線，以能夠支援需要高頻寬傳輸 (bandwidth) 的晶片設計，例如中央處理器和繪圖處理器與高頻寬記憶體間的高密度連線以及高速資料傳輸。嵌入式多晶片互連橋接封裝技術 (embedded multi-die interconnect bridge, EMIB) 提供局部的高密度佈線結構，且相對於廣泛使用的矽中介層 (silicon interposer)，它具有更加穩定的封裝結構以及可使用較小光罩尺寸而備受關注。然而，多晶片封裝 (multi-chip packaging) 在使用嵌入式多晶片互連橋接上需要考慮物理上的連線限制，串擾及能量消耗。
在這篇論文中，我們提出了第一個在考量嵌入式多晶片互連橋接的多晶片封裝平面規劃演算法。我們提出 B*樹以及遞移封閉圖 (transitive closure graph) 的混合資料結構來去表現平面規劃，並基於此結構制定退火 (simulated annealing) 演算法，以有效率地生成符合嵌入式多晶片互連橋接限制的部分遞移封閉圖拓譜結構。我們進一步採用最大生成樹的分割演算法和樹狀結構的分類機制，透過分析嵌入式多晶片互連橋接的拓譜結構來搜索所需的合法平面規劃。實驗結果顯示，與單獨基於遞移封閉圖的退火相比，我們的演算法可以顯著改善面積，總線長以及運算時間。 | zh_TW |
| dc.description.abstract | Modern heterogeneous integration requires dense IO interconnections between chips, such as CPU and memory, to facilitate bandwidth-aware packaging. The embedded multi-die interconnection bridge (EMIB) has attracted much attention recently by providing a high wiring density and stable package structure with a small reticle size. However, EMIB optimization must consider constrained wire orientations and crosstalk. This paper presents the first work on floorplanning for EMIB-based packaging. We first model the floorplanning problem for EMIB-based packaging. Based on a hybrid structure of transitive closure graphs and B*-trees, we present a novel simulated-annealing-based algorithm to generate the desired EMIB-aware floorplans efficiently. We employ maximum-spanning-tree-based partitioning and tree-based classification for already found partial topologies to search for desired solutions more efficiently. Experimental results show that our algorithm can significantly improve the area, total wirelength, and computation time compared with simulated annealing based on TCGs alone. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-06-14T16:04:14Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-06-14T16:04:15Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements iii
Abstract (Chinese) iv Abstract vi List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1 Bandwidth-aware Packaging . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Embedded Multi-die Interconnect Bridge . . . . . . . . . . . . . . . . . . 2 1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Related Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4.1 Silicon-interposer-based Packaging . . . . . . . . . . . . . . . . . . 5 1.4.2 Other Bridge-based MCP Technologies . . . . . . . . . . . . . . . . 6 1.4.3 Related Works on the Floorplanning with Overlap and Adjacency Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 2. Preliminaries 10 2.1 Review of the B*-tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Review of the Transitive Closure Graph . . . . . . . . . . . . . . . . . . . 11 2.3 Wire Connection Model for the EMIB-based Packaging . . . . . . . . . . 12 2.4 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 3. Our Proposed Algorithm 14 3.1 ECG Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Base Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 Initial Topology Creation . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.2 EMIB Legalization . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.3 Base Derivation Process . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.4 Legality-optimized SA . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 Group Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1 Neighboring Topology Generation . . . . . . . . . . . . . . . . . . 25 3.3.2 Tree-based Classification . . . . . . . . . . . . . . . . . . . . . . . 27 3.4 Overall SA Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.1 BT-trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.2 Packing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.3 Perturbation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4.4 Cost Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.5 Silicon Bridge Assignment . . . . . . . . . . . . . . . . . . . . . . . 36 3.4.6 Bridge Overlap Adjustment . . . . . . . . . . . . . . . . . . . . . . 36 Chapter 4. Experimental Results 38 4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.2 Results and Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.1 Comparison with SA-TCG . . . . . . . . . . . . . . . . . . . . . . 40 4.2.2 Effectiveness of MST-based Partition . . . . . . . . . . . . . . . . . 43 4.2.3 Convergence Improvement with Tree-based Classification . . . . . 44 4.2.4 Analysis of Empirical Time Complexity . . . . . . . . . . . . . . . 46 4.2.5 Analysis of the BT-tree Structure . . . . . . . . . . . . . . . . . . 48 4.2.6 Clonclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chapter 5. Conclusions and Future Works 50 5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2.1 Adjacency-relaxed Structure . . . . . . . . . . . . . . . . . . . . . 51 5.2.2 Multi-bridge Connections . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.3 EMIB-aware Placement Problem . . . . . . . . . . . . . . . . . . . 53 Bibliography 54 | - |
| dc.language.iso | en | - |
| dc.subject | 平面規劃 | zh_TW |
| dc.subject | 多晶片封裝 | zh_TW |
| dc.subject | 異質整合 | zh_TW |
| dc.subject | 嵌入式多晶片互連橋接 | zh_TW |
| dc.subject | Embedded Multi-die Interconnection Bridge | en |
| dc.subject | Heterogeneous Integration | en |
| dc.subject | Floorplan | en |
| dc.subject | Multi-chip Packaging | en |
| dc.title | 嵌入式多晶片互連橋接封裝技術之平面規劃 | zh_TW |
| dc.title | Floorplanning for the Embedded Multi-die Interconnect Bridge (EMIB) Package | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 江蕙如;陳宏明;方劭云;黃婷婷 | zh_TW |
| dc.contributor.oralexamcommittee | Hui-Ru Jiang;Hung-Ming Chen;Shao-Yun Fang;Ting-Ting Hwang | en |
| dc.subject.keyword | 異質整合,嵌入式多晶片互連橋接,多晶片封裝,平面規劃, | zh_TW |
| dc.subject.keyword | Heterogeneous Integration,Embedded Multi-die Interconnection Bridge,Multi-chip Packaging,Floorplan, | en |
| dc.relation.page | 58 | - |
| dc.identifier.doi | 10.6342/NTU202300256 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2023-02-08 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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