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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87474完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文 | zh_TW |
| dc.contributor.advisor | Yao-Wen Chang | en |
| dc.contributor.author | 鍾旻軒 | zh_TW |
| dc.contributor.author | Min-Hsuan Chung | en |
| dc.date.accessioned | 2023-06-13T16:10:12Z | - |
| dc.date.available | 2025-02-02 | - |
| dc.date.copyright | 2023-06-13 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-02-04 | - |
| dc.identifier.citation | [1] C++ Library for Generating Constraint or Conforming Delaunay Triangula tions. [Online]. Available: https://www.github.com/artem-ogre/CDT
[2] Fan-Out Chip on Substrate (FOCoS). [Online]. Available: https://ase.aseglobal.com/public/en/technology/focos.html [3] GUC Tapes Out AI/HPC/Networking Platform on TSMC CoWoS® Technology. [Online]. Available: https://www.eetimes.com/guc-tapes-out-ai-hpc-networking-platform-on-tsmc-cowos-technology/ [4] Synopsys and TSMC Accelerate 2.5D/3DIC Designs with CoWos and InFO Certified Design Flows. [Online]. Available: https://news.synopsys.com/2020-08-25-Synopsys-and-TSMC-Accelerate-2-5D-3DIC-Designs-with-Chip\-on-Wafer-on-Substrate-and-Integrated-Fan-Out-Certified-Design-Flows [5] The Chronicle of CoWoS. [Online]. Available: https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm [6] Y.-J. Cai, Simultaneous Pre- and Free-Assignment Net Routing for Multiple Redistribution Layers with Irregular Vias. Graduate Institute of ElectronicsEngineering, National Taiwan University, 2020. [7] Y.-J. Cai, Y. Hsu, and Y.-W. Chang, “Simultaneous Pre- and Free-Assignment Routing for Multiple Redistribution Layers with Irregular Vias,” in Proceedings of ACM/IEEE Design Automation Conference, pp.1147–1152, San Francisco,CA, December 2021. [8] Y.-T. Chen, Obstacle-Avoiding Multiple Redistribution Layer Routing with Ir regular Structures. Graduate Institute of Electronics Engineering, National Taiwan University, 2022. [9] Y.-T. Chen and Y.-W. Chang, “Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures,” in Proceedings of IEEE/ACM In ternational Conference on Computer-Aided Design, pp. 1–6, San Diego, CA, November 2022. [10] J.-W. Fang and Y.-W. Chang, “Area-I/O Flip-Chip Routing for Chip Package Co-Design,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 518–522, San Jose, CA, November 2008. [11] J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 606–611, San Diego, CA, June 2007. [12] J.-W. Fang, I.-J. Lin, Y.-W. Chang, and J.-H. Wang, “A Network-Flow Based RDL Routing Algorithmz for Flip-Chip Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp. 1417–1429, 2007. [13] J.-W. Fang, I.-J. Lin, P.-H. Yuh, Y.-W. Chang, and J.-H. Wang, “A Routing Algorithm for Flip-Chip Design,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 752–757, San Jose, CA, November 2005. [14] J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An Integer-Linear-Programming Based Routing Algorithm for Flip-Chip Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp.98–110, 2009. [15] T. Honda and Y. Kohira, “An Acceleration for Any-Angle Routing Using Quasi- Newton Method on GPGPU,” in Proceedings of IEEE International Sympo sium on Embedded Multicore/Many-Core System-on-Chip, pp. 281–288, Aizu Wakamatsu, Japan, September 2014. [16] Y. Kohira and A. Takahashi, “An Any-Angle Routing Method Using Quasi- Newton Method,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 145–150, Sydney, Australia, February 2012. [17] C.-W. Lin, P.-W. Lee, Y.-W. Chang, C.-F. Shen, and W.-C. Tseng, “An Effi cient Pre-Assignment Routing Algorithm for Flip-Chip Designs,” IEEE Trans actions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 6, pp. 878–889, 2012. [18] C. C. Liu, S.-M. Chen, F.-W. Kuo, H.-N. Chen, E.-H. Yeh, C.-C. Hsieh, L.-H. Huang, M.-Y. Chiu, J. Yeh, T.-S. Lin, T.-J. Yeh, S.-Y. Hou, J.-P. Hung, J.-C. Lin, C.-P. Jou, C.-T. Wang, S.-P. Jeng, and D. C. H. Yu, “High-Performance In tegrated Fan-Out Wafer Level Packaging (InFO-WLP): Technology and System Integration,” in Proceedings of IEEE International Electron Devices Meeting, pp. 14.1.1–14.1.4, San Francisco, CA, December 2012. [19] W.-H. Liu, B. Chen, H.-Y. Chang, G. Lin, and Z.-S. Lin, “Challenges for Au tomating Package Routing,” in Proceedings of ACM International Symposium on Physical Design, pp. 193–194, Canada, March 2022. [20] X. Liu, Y. Zhang, G. K. Yeap, C. Chu, J. Sun, and X. Zeng, “Global Routing and Track Assignment for Flip-Chip Designs,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 90–93, Anaheim, CA, July 2010. [21] S.-R. Nie, Y.-T. Chen, and Y.-W. Chang, “Y-Architecture-Based Flip-Chip Routing with Dynamic Programming-Based Bend Minimization.” in Proceed ings of ACM/IEEE Design Automation Conference, pp. 955–960, San Fran cisco, CA, July 2022. [22] H.-P. Pu, H. Kuo, C. Liu, and C. Douglas, “A Novel Submicron Polymer Re Distribution Layer Technology for Advanced InFO Packaging,” in Proceedings of IEEE Electronic Components and Technology Conference, pp. 45–51, San Diego, CA, June 2018. [23] P. Spindler and F. M. Johannes, “Fast and Accurate Routing Demand Estima tion for Efficient Routability-Driven Placement,” in Proceedings of ACM/IEEE Design, Automation and Test in Europe, pp. 1–6, Nice, France, April 2007. [24] C.-F. Tseng, C.-S. Liu, C.-H. We, and D. Yu, “InFO (Wafer Level Integrated Fan-Out) Technology,” in Proceedings of IEEE Electronic Components and Technology Conference, pp. 1–6, Las Vegas, NV, June 2016. [25] H.-T. Wen, Via-Based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures. Graduate Institute of Electronics Engineering, Na tional Taiwan University, 2020. [26] H.-T. Wen, Y.-J. Cai, Y. Hsu, and Y.-W. Chang, “Via-Based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1–6, San Francisco, CA, July 2020. [27] J. T. Yan and Z. W. Chen, “IO Connection Assignment and RDL Routing for Flip-Chip Designs,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 588–593, Yokohama, Japan, January 2009. [28] T. Yan and M. D. F. Wong, “Correctly Modeling the Diagonal Capacity in Escape Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 2, pp. 285–293, 2012. [29] K. Yang, H. Yao, T.-Y. Ho, K. Xin, and Y. Cai, “AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 12, pp. 3042–3055, 2018. [30] T.-C. Yu, A.-J. Shih, and S.-Y. Fang, “Flip-Chip Routing with I/O Planning Considering Practical Pad Assignment Constraints,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 8, pp. 1921–1932, 2019. [31] M. A. Zapletina, D. A. Zheleznikov, and S. V. Gavrilov, “Improving Pathfinder Algorithm Perfomance for FPGA Routing,” in Proceedings of IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering, pp. 2054–2057, Moscow, Russia, January 2021. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87474 | - |
| dc.description.abstract | 多層重分布層 (redistribution layer) 在先進封裝製程中被廣泛的應用於多晶片間，即訊號在凸塊焊墊 (bump pad)與線路接位置 (I/O pad)間的傳輸。傳統重分布層中的繞線僅允許使用 90 度或者 135 度的轉角來進行繞線。隨著製程的演進，現今的扇出型封裝中(integrated fan-out) 可以使用任意鈍角進行繞線，此製程演進提供更多的繞線可能，通過充分利用任意鈍角的繞線，我們可以得到相對於傳統繞線角度架構下更短的總線長。
在本論文中，我們提出了第一個適用於多層重分布層的任意角度繞線系統。首先，我們給出了一種新穎的，具有精確繞線資源估計的全域繞線模型。接著，我們拓展了文獻中調整連線接點位置的演算法，在多連線系統中快速調整並更新連線接點的位置。最後，我們開發了一種高效的細部繞線系統，在固定接點位置下得到接近最佳解的細部繞線結果。 實驗結果顯示我們的繞線系統相比於目前最先進的單層任意角度繞線器可以得到更高的繞線率，並且，相比於傳統繞線角度的繞線結果，我們的繞線系統在考量非自由配對 (pre-assignment) 與混和式配對(unified-assignment) 的測試連線中，皆可得到不錯的線長優化。 | zh_TW |
| dc.description.abstract | Redistribution layers (RDLs) are widely applied for signal transmissions in advanced packages. Traditional redistribution layer (RDL) routers use only 90- and 135-degree turns for routing. With technological advances, routing in RDLs can be any obtuse angle, leading to larger routing solution spaces and shorter total wirelength.
In this thesis, we propose the first any-angle routing algorithm in the litera ture for multiple RDLs. We first give a novel global routing algorithm with accurate routing resource estimation. A multi-net access point adjustment method is then proposed based on dynamic programming and our partial net separation scheme. Finally, we develop an efficient tile routing algorithm to obtain valid routes with fixed access points. Compared with the state-of-the-art any-angle router, the proposed algorithm can obtain higher routability in the benchmarks. Besides, the experimental results show that our algorithm can achieve a shorter wirelength compared with traditional RDL routers in the pre-assignment (PA) and unified assignment (UA) benchmark sets, respectively. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-06-13T16:10:12Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-06-13T16:10:12Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements iii
Abstract (Chinese) iv Abstract vi List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1 Integrated Fan-Out Structure . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Classification of Traditional RDL Routing . . . . . . . . . . . . . . . . . 3 1.3 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.1 Traditional RDL Routing . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.1.1 Free-Assignment RDL Routing . . . . . . . . . . . . . . . 5 1.3.1.2 Pre-Assignment RDL Routing . . . . . . . . . . . . . . . . 9 1.3.1.3 Unified-Assignment RDL Routing . . . . . . . . . . . . . . 10 1.3.2 Any-Angle Routing . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 2. Preliminaries 16 2.1 Notations and Terminologies . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Any-Angle RDL Routing Constraints . . . . . . . . . . . . . . . . . . . . 17 2.3 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Chapter 3. Our Proposed Algorithm 19 3.1 Global Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.1 Routing Graph Construction . . . . . . . . . . . . . . . . . . . . . 21 3.1.2 Net Order Determination . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.3 Routing Guide Construction . . . . . . . . . . . . . . . . . . . . . 26 3.2 Detailed Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.1 Access Point Adjustment . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.2 Tile Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Chapter 4. Experimental Results 37 4.1 Experimental Environment Setup . . . . . . . . . . . . . . . . . . . . . . 37 4.2 Results and Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.2.1 Comparison with the State-of-the-Art Any-Angle Router . . . . . . 38 4.2.2 Comparison with the traditional RDL Router . . . . . . . . . . . . 39 4.2.3 Empirical Time Complexity . . . . . . . . . . . . . . . . . . . . . . 46 4.2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter 5. Conclusions and Future Work 48 5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Bibliography 52 Publication List 57 | - |
| dc.language.iso | en | - |
| dc.subject | 任意角度繞線 | zh_TW |
| dc.subject | 重分佈層繞線 | zh_TW |
| dc.subject | 實體設計 | zh_TW |
| dc.subject | 不規則矽穿孔結構 | zh_TW |
| dc.subject | 扇出型封裝 | zh_TW |
| dc.subject | Physical Design | en |
| dc.subject | Redistribution Layer Routing | en |
| dc.subject | Any-Angle Routing | en |
| dc.subject | Integrated Fan-Out | en |
| dc.subject | Irregular Via Structure | en |
| dc.title | 考量任意繞線角度之多層重分佈層不規則矽穿孔繞線系統 | zh_TW |
| dc.title | Any-Angle Routing for Redistribution Layers in 2.5D IC | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 江蕙如;方劭云;黃婷婷;陳宏明 | zh_TW |
| dc.contributor.oralexamcommittee | Hui-Ru Jiang;Shao-Yun Fang;Ting-Ting Hwang;Hung-Ming Chen | en |
| dc.subject.keyword | 扇出型封裝,實體設計,任意角度繞線,重分佈層繞線,不規則矽穿孔結構, | zh_TW |
| dc.subject.keyword | Physical Design,Redistribution Layer Routing,Any-Angle Routing,Integrated Fan-Out,Irregular Via Structure, | en |
| dc.relation.page | 57 | - |
| dc.identifier.doi | 10.6342/NTU202300254 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2023-02-08 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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