請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87293完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文 | zh_TW |
| dc.contributor.advisor | Yao-Wen Chang | en |
| dc.contributor.author | 陳威旭 | zh_TW |
| dc.contributor.author | Wei-Hsu Chen | en |
| dc.date.accessioned | 2023-05-18T16:53:15Z | - |
| dc.date.available | 2025-12-31 | - |
| dc.date.copyright | 2023-05-14 | - |
| dc.date.issued | 2022 | - |
| dc.date.submitted | 2002-01-01 | - |
| dc.identifier.citation | [1] X.-Y. Bao, H. Yi, C. Bencher, L.-W. Chang, H. Dai, Y. Chen, P.-T. J. Chen, and H.-S. P. Wong, “SRAM, NAND, DRAM Contact Hole Patterning Using Block Copolymer Directed Self-Assembly Guided by Small Topographical Templates,” in Proceedings of IEEE International Electron Devices Meeting, pp. 7.7.1–7.7.4, 2011. [2] I. S. Bustany, D. Chinnery, J. R. Shinnerl, and V. Yutsis, “ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement,” in Proceedings of ACM International Symposium on Physical Design, p. 157–164, 2015. [3] J.-B. Chang, H. K. Choi, A. F. Hannon, A. Alexander-Katz, C. A. Ross, and K. K. Berggren, “Design Rules for Self-Assembled Block Copolymer Patterns Using Tiled Templates,” Nature Communications, no. 5, 2014. [4] Y.-W. Chang and Y.-T. Chang, “An Architecture-Driven Metric for Simultaneous Placement and Global Routing for FPGAs,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 567—-572, 2000. [5] Y. Du, Z. Xiao, M. D. F. Wong, H. Yi, and H.-S. P. Wong, “DSA-Aware Detailed Routing for Via Layer Optimization,” in Proceedings of International Society for Optics and Photonics, vol. 9049, pp. 548 – 555, 2014. [6] K.-S. Hu, M.-J. Yang, T.-C. Yu, and G.-C. Chen, “ICCAD-2020 CAD Contest in Routing with Cell Movement,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 1–4, 2020. [7] S.-J. Jeong, J. Y. Kim, B. H. Kim, H.-S. Moon, and S. O. Kim, “Directed Self-Assembly of Block Copolymers for Next Generation Nanolithography,” Materials Today, vol. 16, no. 12, pp. 468–476, 2013. [8] J. Kuang, E. F. Young, and B. Yu, “Incorporating Cut Redistribution with Mask Assignment to Enable 1D Gridded Design,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 1–8, 2016. [9] Z.-W. Lin and Y.-W. Chang, “Cut Redistribution with Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 12, pp. 2066–2079, 2017. [10] Z.-W. Lin and Y.-W. Chang, “Detailed Placement for Two-Dimensional Directed Self-Assembly Technology,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1–6, 2017. [11] Y. Ma, J. A. Torres, G. Fenger, Y. Granik, J. Ryckaert, G. Vanderberghe, J. Bekaert, and J. Word, “Challenges and Opportunities in Applying Grapho- Epitaxy DSA Lithography to Metal Cut and Contact/Via Applications,” in Proceedings of 30th European Mask and Lithography Conference, vol. 9231, pp. 222 – 231, 2014. [12] J. Ou, B. Cline, G. Yeric, and D. Z. Pan, “Efficient DSA-DP Hybrid Lithography Conflict Detection and Guiding Template Assignment,” in Proceedings of International Society for Optics and Photonics, vol. 10148, pp. 86 – 94, 2017. [13] J. Ou, B. Yu, X. Xu, J. Mitra, Y. Lin, and D. Z. Pan, “DSAR: DSA Aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment,” in Proceedings of ACM International Symposium on Physical Design, p. 91–98, 2017. [14] Y.-H. Su and Y.-W. Chang, “DSA-Compliant Routing for Two-Dimensional Patterns Using Block Copolymer Lithography,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 1–8, 2016. [15] Y.-H. Su and Y.-W. Chang, “VCR: Simultaneous Via-Template and Cut-Template-Aware Routing for Directed Self-Assembly Technology,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 1–8, 2016. [16] Z.-L. Wang and Y.-W. Chang, “Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 1–7, 2019. [17] H.-S. P.Wong, C. Bencher, H. Yi, X.-Y. Bao, and L.-W. Chang, “Block Copolymer Directed Self-Assembly Enables Sublithographic Patterning for Device Fabrication,” in Proceedings of International Society for Optics and Photonics, vol. 8323, pp. 26 – 32, 2012. [18] K.-H. Wu and S.-Y. Fang, “Simultaneous Template Assignment and Layout Decomposition Using Multiple BCP Materials in DSA-MP Lithography,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 239–244, 2017. [19] Z. Wu, Q. Yao, S. Zang, and J. Xie, “Directed Self-Assembly of Ultrasmall Metal Nanoclusters,” ACS Materials Letters, vol. 1, no. 2, pp. 237–248, 2019. [20] Z. Xiao, Y. Du, M. D. Wong, and H. Zhang, “DSA Template Mask Determination and Cut Redistribution for Advanced 1D Gridded Design,” in Proceedings of International Society for Optics and Photonics, pp. 155 – 162, 2013. [21] H.-J. Yu and Y.-W. Chang, “DSA-Friendly Detailed Routing Considering Double Patterning and DSA Template Assignments,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1–6, 2018. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/87293 | - |
| dc.description.abstract | 二維定向自我組裝 (two-dimensional directed self-assembly) 是一種用於次 2 奈米及以下的新興光刻技術。我們在使用二維定向自我組裝技術的過程中，可以通過決定雙重點狀圖樣 (double post) 的方向來引導嵌段共聚物形成可行的二維引導模板圖樣。在本篇論文中，我們提出首個方法來解決二維定向自我組裝電路之同時擺置與繞線的問題。首先，我們提出一種新穎的二維定向自我組裝結構圖來對可行的二維引導模板圖樣進行建模，該圖模型能於指定一個雙重點狀圖樣的方向後，在固定時間內完成圖模型的更新，以及能夠在線性時間內將圖形路徑轉換成符合定向自我組裝規範的繞線路徑。其次，我們基於圖模型提出一個二維定向自我組裝之同時擺置與繞線的演算法，該演算法包含有二維定向自我組裝單元放置時使用的基於廣播的成本函數，以及一個基於圖模型的方案來生成符合定向自我組裝規範的繞線。最終，我們使用強有效區域的特性來最小化在最終布局中金屬線末端之切斷點的數量。實驗結果顯示，我們的演算法可以高效率的生成具有高可繞性及零個雙重點狀圖樣之方向衝突的二維定向自我組裝電路之擺置與繞線的結果。 | zh_TW |
| dc.description.abstract | Two-dimensional directed self-assembly (2D-DSA) is an emerging lithography technology for the sub-2nm process node and beyond. We can determine the orientations of double posts to guide block copolymers to form feasible 2D guiding template patterns by the 2D-DSA process. In this thesis, we present the first work to handle the 2D-DSA simultaneous placement and routing problem. We first propose a novel 2D-DSA structure graph to model the feasible 2D-DSA guiding templates with a constant-time update scheme for each double post assignment and a linear-time scheme for a graph path transforming into a DSA-compliant routing path. Based on the graph modeling, we then present an algorithm flow for 2D-DSA simultaneous placement and routing, with a broadcast-based cost function for 2D-DSA cell placement and a graph-based scheme for DSA-compliant routing. Finally, we employ the strongly effective region property to minimize the line-end cuts in the final layout. Experimental results show that our algorithm can efficiently generate a 2D-DSA placement and routing solution with high routability and zero double-post conflict. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-05-18T16:53:15Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-05-18T16:53:15Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements iii Abstract (Chinese) iv Abstract vi List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1 Two-Dimensional Directed Self-Assembly . . . . . . . . . . . . . . . . . . 1 1.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2. Preliminaries 9 2.1 Self-stopping Line-end Cut . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 3. 2D-DSA Structure Graphical Model 13 3.1 The Structure of the Graphical Model . . . . . . . . . . . . . . . . . . . . 13 3.1.1 Tile Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.2 The Components of the Graphical Model . . . . . . . . . . . . . . 15 3.1.3 The Characteristics of the Edges . . . . . . . . . . . . . . . . . . . 15 3.1.4 The Graphic Meaning of the Edges . . . . . . . . . . . . . . . . . . 17 3.2 Edge Deleting Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.1 Single Double Post Checking . . . . . . . . . . . . . . . . . . . . . 19 3.2.2 Adjacent Double Post Checking . . . . . . . . . . . . . . . . . . . 21 3.3 Additional Double Post Assigning Rule . . . . . . . . . . . . . . . . . . . 24 3.4 Track Parameter for Detailed Routing . . . . . . . . . . . . . . . . . . . . 25 Chapter 4. Our Proposed Algorithm 27 4.1 Algorithm Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 Greedy Cell Choosing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3 2D-DSA Structure-aware Placement . . . . . . . . . . . . . . . . . . . . . 30 4.3.1 The Broadcast Rule of the Graph Node . . . . . . . . . . . . . . . 30 4.3.2 Our Cost Function . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 Graph-based Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.5 Graphical Model Updating . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.6 Cut Pattern Assigning . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chapter 5. Experimental Results 39 5.1 Experimental Settings & Benchmarks . . . . . . . . . . . . . . . . . . . . 39 5.2 General Cases Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3 Simple Cases Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chapter 6. Conclusions and Future Work 50 Bibliography 54 | - |
| dc.language.iso | en | - |
| dc.subject | 實體設計 | zh_TW |
| dc.subject | 製造設計 | zh_TW |
| dc.subject | 二維定向自我組裝 | zh_TW |
| dc.subject | 擺置 | zh_TW |
| dc.subject | 繞線 | zh_TW |
| dc.subject | Two-Dimensional Directed Self-Assembly | en |
| dc.subject | Design for Manufacturing | en |
| dc.subject | Detailed Placement | en |
| dc.subject | Physical Design | en |
| dc.subject | Detailed Routing | en |
| dc.title | 基於圖論針對二維定向自我組裝技術之電路同時擺置與繞線 | zh_TW |
| dc.title | Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 黃婷婷;張原豪;陸寶森;江蕙如 | zh_TW |
| dc.contributor.oralexamcommittee | Ting-Ting Hwang;Yuan-Hao Chang;Peter Luh;Hui-Ru Jiang | en |
| dc.subject.keyword | 實體設計,二維定向自我組裝,製造設計,擺置,繞線, | zh_TW |
| dc.subject.keyword | Physical Design,Two-Dimensional Directed Self-Assembly,Design for Manufacturing,Detailed Placement,Detailed Routing, | en |
| dc.relation.page | 57 | - |
| dc.identifier.doi | 10.6342/NTU202202297 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2022-10-04 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2025-12-31 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-111-1.pdf 授權僅限NTU校內IP使用（校園外請利用VPN校外連線服務） | 2.48 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。