Skip navigation

DSpace

機構典藏 DSpace 系統致力於保存各式數位資料(如:文字、圖片、PDF)並使其易於取用。

點此認識 DSpace
DSpace logo
English
中文
  • 瀏覽論文
    • 校院系所
    • 出版年
    • 作者
    • 標題
    • 關鍵字
    • 指導教授
  • 搜尋 TDR
  • 授權 Q&A
    • 我的頁面
    • 接受 E-mail 通知
    • 編輯個人資料
  1. NTU Theses and Dissertations Repository
  2. 工學院
  3. 材料科學與工程學系
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/86977
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor莊東漢zh_TW
dc.contributor.advisorTung-Han Chuangen
dc.contributor.author邱冠諭zh_TW
dc.contributor.authorKuan-Yu Chiuen
dc.date.accessioned2023-05-02T17:11:48Z-
dc.date.available2023-11-09-
dc.date.copyright2023-05-02-
dc.date.issued2023-
dc.date.submitted2023-01-08-
dc.identifier.citation[1] Cheng, H. C., Chiang, K. N., & Lee, M. H. (1998). An alternative local/global finite element approach for ball grid array typed packages. ASME Journal of Electronic Packaging, 120, 129-134.
[2] Chiang, K. N., & Chen, W. L. (1998). Electronic packaging reflow shape prediction for the solder mask defined ball grid array.
[3] Nishimura, Y., Mochizuki, E., & Takahashi, Y. (2005). Development of a next-generation IGBT module using a new insulating substrate. Fuji Electric Review, 51(2), 52-56.
[4] Iwamuro, N., & Laska, T. (2017). IGBT history, state-of-the-art, and future prospects. IEEE Transactions on Electron Devices, 64(3), 741-752.
[5] Nishimura, Y., Mochizuki, E., & Takahashi, Y. (2005). Development of a next-generation IGBT module using a new insulating substrate. Fuji Electric Review, 51(2), 52-56.
[6] K. Yamagami et al., “Transistors,” Japanese Patent S4 721 739, Jun. 19, 1968.
[7] Baliga, B. J. (1979). Enhancement-and depletion-mode vertical-channel MOS gated thyristors. Electronics Letters, 15(20), 645-647.
[8] Plummer, J. D. (1980). U.S. Patent No. 4,199,774. Washington, DC: U.S. Patent and Trademark Office.
[9] H. W. Becke and C. F. Wheatley, Jr., “Power MOSFET with an anode region,” U.S. Patent 4 364 073, Dec. 14, 1982.
[10] Russell, J. P., Goodman, A. M., Goodman, L. A., & Neilson, J. M. (1983). The COMFET—A new high conductance MOS-gated device. IEEE Electron Device Letters, 4(3), 63-65.
[11] Baliga, B. J., Adler, M. S., Gray, P. V., Love, R. P., & Zommer, N. (1982, December). The insulated gate rectifier (IGR): A new power switching device. In 1982 International Electron Devices Meeting (pp. 264-267). IEEE.
[12] Nakagawa, A., Ohashi, H., Kurata, M., Yamaguchi, H., & Watanabe, K. (1984, December). Non-latch-up 1200V 75A bipolar-mode MOSFET with large ASO. In 1984 International Electron Devices Meeting (pp. 860-861). IEEE.
[13] Goodman, A. M., Russell, J. P., Goodman, L. A., Nuese, C. J., & Neilson, J. M. (1983, December). Improved COMFETs with fast switching speed and high-current capability. In 1983 International Electron Devices Meeting (pp. 79-82). IEEE.
[14] Harada, M., Minato, T., Takahashi, H., Nishihara, H., Inoue, K., & Takata, I. (1994, May). 600 V trench IGBT in comparison with planar IGBT-an evaluation of the limit of IGBT performance. In Proceedings of the 6th International Symposium on Power Semiconductor Devices and ICs (pp. 411-416). IEEE.
[15] Otsuki, M., Momota, S., Nishiura, A., & Sakurai, K. (1993, May). The 3rd generation IGBT toward a limitation of IGBT performance. In [1993] Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs (pp. 24-29). IEEE.
[16] Kitagawa, M., Omura, I., Hasegawa, S., Inoue, T., & Nakagawa, A. (1993, December). A 4500 V injection enhanced insulated gate bipolar transistor (IEGT) operating in a mode similar to a thyristor. In Proceedings of ieee international electron devices meeting (pp. 679-682). IEEE.
[17] Takahashi, H., Haruguchi, H., Hagino, H., & Yamada, T. (1996, May). Carrier stored trench-gate bipolar transistor (CSTBT)-a novel power device for high voltage application. In 8th International Symposium on Power Semiconductor Devices and ICs. ISPSD'96. Proceedings (pp. 349-352). IEEE.
[18] Laska, T., Pfirsch, F., Hirler, F., Niedermeyr, J., Schaffer, C., & Schmidt, T. (1998, June). 1200 V-trench-IGBT study with square short circuit SOA. In Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No. 98CH36212) (pp. 433-436). IEEE.
[19] Nakagawa, A., Nakamura, S., & Shinohe, T. (1987, June). Rapid Convergence Bipolar-MOS Composite Device Model-Tonadder-And Its Application To Bipolar-Mode MOSFETs (IGBT). In [1987] NASECODE V: Proceedings of the Fifth International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits (pp. 295-300). IEEE.
[20] Iwamuro, N., Okamoto, A., Tagami, S., & Motoyama, H. (1991). Numerical analysis of short-circuit safe operating area for p-channel and n-channel IGBTs. IEEE transactions on electron devices, 38(2), 303-309.
[21] Omura, I., & Nakagawa, A. (1992, May). 4.5 kV GTO turn-off failure analysis under an inductive load including snubber, gate circuit and various parasitics. In Proceedings of the 4th International Symposium on Power Semiconductor Devices and Ics (pp. 112-117). IEEE.
[22] Miller, G., & Sack, J. (1989, June). A new concept for a non punch through IGBT with MOSFET like switching characteristics. In 20th Annual IEEE Power Electronics Specialists Conference (pp. 21-25). IEEE.
[23] Laska, T., Munzer, M., Pfirsch, F., Schaeffer, C., & Schmidt, T. (2000, May). The field stop IGBT (FS IGBT). A new power device concept with a great improvement potential. In 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No. 00CH37094) (pp. 355-358). IEEE.
[24] Kilby, J. S. (1976). Invention of the integrated circuit. IEEE Transactions on electron devices, 23(7), 648-654.
[25] Haisma, J., & Spierings, G. A. C. M. (2002). Contact bonding, including direct-bonding in a historical and recent context of materials science and technology, physics and chemistry: historical review in a broader scope and comparative outlook. Materials Science and Engineering: R: Reports, 37(1-2), 1-60.
[26] Bader, S., Gust, W., & Hieber, H. (1995). Rapid formation of intermetallic compounds interdiffusion in the Cu-Sn and Ni-Sn systems. Acta metallurgica et materialia, 43(1), 329-337.
[27] Jacobson, D. M., & Humpston, G. (1992). Diffusion soldering. Soldering & Surface Mount Technology.
[28] Aasmundtveit, K. E., Tollefsen, T. A., Luu, T. T., Duan, A., Wang, K., & Hoivik, N. (2013, September). Solid-Liquid Interdiffusion (SLID) bonding—Intermetallic bonding for high temperature applications. In 2013 Eurpoean Microelectronics Packaging Conference (EMPC) (pp. 1-6). IEEE.
[29] Kim, J. Y., Park, S. W., Yoon, J. Y., Kim, H. Y., Lee, D. Y., Kim, G. T., ... & Kang, E. G. (2004). The characteristics of joints with Indium-silver alloy using diffusion soldering method. MRS Online Proceedings Library Archive, 817.
[30] A. Munding, A. Kaiser, P. Benkart, E. Kohn, A. Heittmann, H. Hübner and U. Ramacher, “Scaling aspects of microjoints for 3D chip interconnects,” Solid-State Device Research Conference, 2006. pp. 262 - 265.
[31] P. Ramm, M.J. Wolf, A. Klumpp, R. Wieland, B. Wunderle, B. Michel and H. Reichl, “Through silicon via technology - processes and reliability for wafer-level 3D system integration,” Electronic Components and Technology Conference, 2008. pp. 841 - 846.
[32] R. Agarwal, W. Zhang, P. Limaye, R. Labie, B. Dimcic, A. Phommahaxay, and P. Soussan, “Cu/Sn Microbumps Interconnect for 3D TSV Chip Stacking,” ECTC 2010, pp. 858 - 863.
[33] R. Agarwal, W. Zhang, P. Limaye and W. Ruythooren, “High Density Cu-Sn TLP Bonding for 3D Integration,” ECTC 2009, pp. 345 - 349.
[34] H.A. Mustain, W.D. Brown and S.S. Ang, “Transient Liquid Phase Die Attach for High-Temperature Silicon Carbide Power Devices,” Components and Packaging Technologies 2010, pp. 563 - 570.
[35] L. Menager, M. Soueidan, B. Allard, V. Bley and B. Schlegel, “A Lab-Scale Alternative Interconnection Solution of Semiconductor Dice Compatible with Power Modules 3-D Integration,” Power Electronics, IEEE Transactions on (Volume:25 , Issue: 7 ), July 2010, pp. 1667 - 1670.
[36] K. Guth, D. Siepe, J. Görlich, H. Torwesten, R. Roth, F. Hille and F. Umbach, “New Assembly and Interconnects beyond Sintering Methods,” Proceedings of PCIM, pp. 232-237 (2010).
[37] Yoon, S. W., Glover, M. D., & Shiozaki, K. (2012). Nickel–tin transient liquid phase bonding toward high-temperature operational power electronics in electrified vehicles. IEEE Transactions on Power Electronics, 28(5), 2448-2456.
[38] Jacobson, D. M., & Humpston, G. (1992). Diffusion soldering. Soldering & Surface Mount Technology.
[39] Kovacs, I., & Vörös, G. (1996). On the mathematical description of the tensile stress-strain curves of polycrystalline face centered cubic metals. International journal of plasticity, 12(1), 35-43.
[40] Rowden, B., Mantooth, A., Ang, S., Lostetter, A., Hornberger, J., & McPherson, B. (2009, January). High temperature SiC power module packaging. In ASME International Mechanical Engineering Congress and Exposition (Vol. 43789, pp. 85-90).
[41] Pürschel, M., & Röschlau, K. (2011). Diffusion soldering for automotive power MOSFETs offers the first 100% lead free die attach. In Proceedings of the 2011 14th European Conference on Power Electronics and Applications (pp. 1-7). IEEE.
[42] Karakaya, I., & Thompson, W. T. (1987). The Ag-Sn (silver-tin) system. Bulletin of Alloy Phase Diagrams, 8(4), 340-347.
[43] H. Baker, ASM Handbook of alloy phase diagram vol. 3: ASM international:Materials Park, 1992.
[44] Munding, A., Kaiser, A., Benkart, P., Kohn, E., Heittmann, A., Hubner, H., & Ramacher, U. (2006, September). Scaling aspects of microjoints for 3D chip interconnects. In 2006 European Solid-State Device Research Conference (pp. 262-265). IEEE.
[45] Kanata, T., Nishiwaki, K., & Hamada, K. (2010, June). Development trends of power semiconductors for hybrid vehicles. In The 2010 International Power Electronics Conference-ECCE ASIA- (pp. 778-782). IEEE.
[46] Yoon, S. W., Glover, M. D., & Shiozaki, K. (2012). Nickel–tin transient liquid phase bonding toward high-temperature operational power electronics in electrified vehicles. IEEE Transactions on Power Electronics, 28(5), 2448-2456.
[47] Printed Circuits Handbook, Editor Clyde F. Coombs, Jr., 4th edition, McGraw-Hill., New York, 1995.
[48] Yamada, Y., Takaku, Y., Yagi, Y., Nishibe, Y., Ohnuma, I., Sutou, Y., ... & Ishida, K. (2006). Pb-free high temperature solders for power device packaging. Microelectronics Reliability, 46(9-11), 1932-1937.
[49] Liu, X., Haque, S., Wang, J., & Lu, G. Q. (2000, February). Packaging of integrated power electronics modules using flip-chip technology. In APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No. 00CH37058) (Vol. 1, pp. 290-296). IEEE.
[50] Mei, Z., Ahmad, M., Hu, M., & Ramakrishna, G. (2005, May). Kirkendall voids at Cu/solder interface and their effects on solder joint reliability. In Proceedings Electronic Components and Technology, 2005. ECTC'05. (pp. 415-420). IEEE.
[51] Munding, A., Kaiser, A., Benkart, P., Kohn, E., Heittmann, A., Hubner, H., & Ramacher, U. (2006, September). Scaling aspects of microjoints for 3D chip interconnects. In 2006 European Solid-State Device Research Conference (pp. 262-265). IEEE.
[52] Ramm, P., Wolf, M. J., Klumpp, A., Wieland, R., Wunderle, B., Michel, B., & Reichl, H. (2008, May). Through silicon via technology—processes and reliability for wafer-level 3D system integration. In 2008 58th Electronic Components and Technology Conference (pp. 841-846). IEEE.
[53] Agarwal, R., Zhang, W., Limaye, P., Labie, R., Dimcic, B., Phommahaxay, A., & Soussan, P. (2010, June). Cu/Sn microbumps interconnect for 3D TSV chip stacking. In 2010 Proceedings 60th electronic components and technology conference (ECTC) (pp. 858-863). IEEE.
[54] Agarwal, R., Zhang, W., Limaye, P., & Ruythooren, W. (2009, May). High density Cu-Sn TLP bonding for 3D integration. In 2009 59th electronic components and technology conference (pp. 345-349). IEEE.
[55] T.B. Massalski, P.R. Subramanian and L. Kacprzak, "Binary Alloy Phase Diagrams," ASM International, 1990.
[56] Dreike P L, Fleetwood D M, King D B, et al. An overview of high-temperature electronic device technologies and potential applications[J]. IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 1994, 17(4): 594-609.
[57] Kenneth FG, Ronald DS. Interaction of radiation with semiconductor devices[M] //Cressler J D, Mantooth H A. Extreme Environment Electronics.Boca Raton: CRC Press, 2017: 79- 91.
[58] BayererR, HerrmannT, LichtT, et al. Model forpower cycling lifetime of IGBT modules: various factors influencing lifetime[C] //5th International Conference on Integrated Power Electronics Systems, March 11-13, 2008, Nuremberg, Germany. Hannover: VDE Verlag Gmbh, 2008: 1- 6.
[59] 任辉, 张宏强, 王文淦, 贾强, 彭鹏, & 邹贵生. (2021). 纳米金属颗粒焊膏低温烧结连接及其接头可靠性研究进展. 中国激光, 48(8), 0802011.
[60] Siow K S. Are sintered silver joints ready for use as interconnect material in microelectronic packaging?[J]. Journal of Electronic Materials, 2014, 43(4): 947-961.
[61] LuD, Wong CP. Materials for advanced packaging[M]. Boston: Springer, 2009.
[62] Ide E, Angata S, Hirose A, et al. Metal-metal bonding process using Ag metallo-organic nanoparticles[J]. Acta Materialia, 2005, 53(8): 2385-2393.
[63] Zhang H Q, Wang W G, Bai H L, et al. Microstructural and mechanical evolution of silver sintering die attach for SiC power devices during high temperature applications[J]. Journal of Alloys and Compounds, 2019, 774: 487-494.
[64] Wang W G, Zou G S, Jia Q, et al. Mechanical properties and microstructure of low temperature sintered joints using organic-free silver nanostructured film for die attachment of SiC power electronics[J]. Materials Science and Engineering: A, 2020, 793: 139894.
[65] 果世駒. 粉末燒結理論[M]. 北京: 冶金工業出版社, 1998. Guo SJ. Powder metallurgy sintering theory[M]. Beijing: Metallurgical Industry Press, 1998.
[66] Kang S JL. Grain growth and densification in porous materials[M] // Kang S J L. Sintering. Amsterdam: Elsevier, 2005: 145- 170.
[67] 阮建明, 黃培云. 粉末冶金原理[M]. 北京: 機械工業出版社, 2012.
[68] Temperature cycling, JESD22-A104-B, JEDEC, July 2000.
[69] Jacobson, D. M., & Humpston, G. (1992). Diffusion soldering. Soldering & Surface Mount Technology.
[70] Runyan, W. R. (1965). Silicon semiconductor technology/texas instruments electronics series/(Book on silicon semiconductor technology including manufacturing processes, casting and diffusion techniques, crystal growth and orientation and physical, optical and electrical properties). NEW YORK, MCGRAW-HILL BOOK CO., 1965. pp. 223-229.
-
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/86977-
dc.description.abstract在功率元件與模組晶片與產品尺寸持續縮小化,卻同時需要具備高效能、低功耗的趨勢下,先進封裝技術的研究成為最有潛力的研究領域,然而先進封裝技術的發展受限於接合介面的介金屬化合物成長、熱影響、可靠度、電性等...相關的問題,使得在近年來BGBM(Backside Grinding & Backside Metallization)製程晶片與固液擴散接合 (SLID)引起了學術界與產業界的極大興趣,主要是因為在接合領域可以達到「低溫接合,高溫應用」的效果,能夠作為一種可靠的接合方法。

本研究在真空環境中通過 SLID 技術將以130℃蒸鍍優化的 BGBM wafer (Si/Ti/Ni/Ag/Sn,厚度分別為1, 3, 5, 14 KÅ)於DBC基板(Au/Pd/Ni/Cu/Al2O3,厚度分別為1, 0.75, 45, 750 KÅ)上接合,通過 SEM/EDX 觀察接合界面處的擴散現象,接合系統實現了具有超過 7.91 MPa 優異的平均接合強度且定義明確的層狀結合結構,觀察到Ag3Sn、Ni3Sn4和Ni3Sn2的介金屬化合物在 Si/Ti/Ni/Ag/Sn 晶片和 DBC 基板的接合界面之間,證明了SLID 接合系統是一項非常有利被應用於低溫接合中的材料,這項創新的接合技術在功率元件與模組、IGBT、微機電產業(MEMS)、光電產業、傳感器、對熱敏感之元件、3D IC以及各個領域的互聯應用顯示出巨大的潛力。

由於更低溫度的接合與實現更高的可靠度有利於技術的發展與提升產業利用性,因此將擴散焊接溫度進一步降低到 250°C,這將有利於更低的製程溫度與更低元件耐熱需求,有降低成本的優勢,完成接合的樣品投入嚴謹的可靠度驗證(高溫貯存試驗 High Temperature Storage Test 125°C、高溫水蒸汽壓力試驗Pressure Cook Test 121°C/100%R.H./2atm、溫度循環試驗Temperature Cycling Test -55°C - 125°C 溫變率大於20℃/min以上)後,藉以研究對接合處微結構演變的影響,通過 SEM/EDX 觀察分析接合界面處的介金屬化合物變化狀況,驗證了接合的可靠性。

此外本研究透過BGBM Si/Ti/Ni/Sn 與BGBM Si/Ti/Ni/Ag/Sn金屬化矽晶片與Ni/Pd/Au表面處理的DBC氧化鋁基板通過固液擴散接合,驗證在接合中間層加入Ag層所形成的Ag3Sn介金屬化合物夾層,可以有效防止接合介面處出現的孔洞和縫隙,在 Si/Ti/Ni/Ag/Sn 晶片和 DBC 襯底之間的接合界面上確定的介金屬化合物的相為Ag3Sn、Ni3Sn4 和 Ni3Sn2,推力測試的平均接合強度約為 19.75 MPa,最大接合強度達到 35.24 MPa。

考慮降低材料成本的可能性,採用BGBM Si/Ti/Ni/Cu/Sn 與Si/Ti/Ni/Cu/Ag/Sn DBC金屬化矽晶片與Ni/Pd/Au表面處理的DBC氧化鋁基板通過固液擴散接合進行探討。

本研究也加入了奈米銀燒接合技術試驗做相關系列的接合研究與探討,期望在學術界與產業界的能夠有進一步的貢獻。
zh_TW
dc.description.abstractUnder the trend that the size of power components and module chips and products continues to shrink, but at the same time need to have high performance and low power consumption, the research of advanced packaging technology has become the most potential research field, but the development of advanced packaging technology is limited Problems related to the growth of intermetallic compounds at the bonding interface, thermal influence, reliability, electrical properties, etc. have made BGBM (Backside Grinding & Backside Metallization) process wafers and solid-liquid diffusion bonding (SLID) aroused academic circles in recent years. The great interest in the industry is mainly because the effect of "low-temperature bonding, high-temperature application" can be achieved in the field of bonding, and it can be used as a reliable bonding method.

In this study, optimized BGBM wafers (Si/Ti/Ni/Ag/Sn, with thicknesses of 1, 3, 5, and 14 KÅ) were deposited on DBC substrates (Au/Pd/ Ni/Cu/Al2O3 with thicknesses of 1, 0.75, 45, 750 KÅ) were bonded, and the diffusion phenomenon at the bonding interface was observed by SEM/EDX. The bonding system achieved an excellent average bonding strength of more than 7.91 MPa and a well-defined The layered bonding structure, intermetallic compounds of Ag3Sn, Ni3Sn4 and Ni3Sn2 were observed between the bonding interface of Si/Ti/Ni/Ag/Sn wafer and DBC substrate, proving that the SLID bonding system is a very favorable method to be applied at low-temperature Materials in bonding, this innovative bonding technology has shown great promise in power components and modules, IGBTs, MEMS, optoelectronics, sensors, heat-sensitive components, 3D ICs, and interconnection applications in potential various fields.
Since lower temperature bonding and higher reliability are conducive to the development of technology and the improvement of industrial applicability, the diffusion soldering temperature is further reduced to 250°C, which will benefit lower process temperature and lower heat resistance of components demand, has the advantage of reducing costs, and the completed joint samples are put into rigorous reliability verification (high-temperature storage test 125°C, high-temperature water vapor pressure test Pressure Cook Test 121°C/100%R.H./2atm, temperature cycle After testing the Temperature Cycling Test -55°C - 125°C (temperature change rate greater than 20°C/min), it is used to study the influence on the microstructure evolution of the joint, and the change of the intermetallic compound at the joint interface is observed and analyzed by SEM/EDX, the reliability of the bonding was verified.

In addition, this study uses solid-liquid diffusion bonding of BGBM Si/Ti/Ni/Sn and BGBM Si/Ti/Ni/Ag/Sn metalized silicon wafers and Ni/Pd/Au surface-treated DBC alumina substrates to verify that in the middle of bonding The Ag3Sn intermetallic compound interlayer formed by adding the Ag layer can effectively prevent holes and gaps at the joint interface, and the intermetallic determined on the joint interface between the Si/Ti/Ni/Ag/Sn wafer and the DBC substrate The phases of the compound are Ag3Sn, Ni3Sn4, and Ni3Sn2, the average joint strength of the thrust test is about 19.75 MPa, and the maximum joint strength reaches 35.24 MPa.

Considering the possibility of reducing the cost of materials, BGBM Si/Ti/Ni/Cu/Sn and Si/Ti/Ni/Cu/Ag/Sn DBC metalized silicon wafers and DBC alumina substrates with Ni/Pd/Au surface treatment were adopted Solid-liquid diffusion bonding.
This study also joined the nano-silver firing bonding technology experiment to do a series of bonding research and discussion, hoping to make further contributions in academia and industry.
en
dc.description.provenanceSubmitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-05-02T17:11:48Z
No. of bitstreams: 0
en
dc.description.provenanceMade available in DSpace on 2023-05-02T17:11:48Z (GMT). No. of bitstreams: 0en
dc.description.tableofcontents目錄 VI
圖目錄 IX
表目錄 XIV

第一章 前言 1
1.1 研究背景 1
1.1.1 電子構裝重要性 1
1.1.2 功率半導體的發展 3
1.1.3 功率元件IGBT的介紹 7
1.2 研究動機與目的 13

第二章 理論基礎與文獻回顧 15
2.1 絕緣柵雙極晶體管(Insulated gate bipolar transistor, IGBT) 的發展[4] 15
2.1.1 功率半導體IGBT的應用 15
2.1.2 功率半導體IGBT的演進 16
2.2 先進封裝BGBM(Backside Grinding & Backside Metallization)介紹 24
2.3 半導體接合技術的發展 26
2.4 固液擴散接合(Solid liquid Interdiffusion Bonding) 27
2.5 介金屬化合物(Intermetallic Compound)介紹 30
2.5.1 Ag-Sn SLID接合 30
2.5.2 Ni-Sn SLID接合 31
2.5.3 Cu-Sn SLID接合 33
2.6 奈米金屬顆粒焊膏低溫燒結連接介紹[59] 35
2.6.1 奈米金屬顆粒焊膏燒結連接機理 36
2.6.2 奈米金屬燒結焊膏顆粒尺寸 37
2.6.3 奈米金屬燒結焊膏燒結過程 38

第三章 實驗方法 40
3.1 實驗流程 40
3.1.1 總體實驗流程圖 40
3.1.2 實驗製程示意圖 41
3.2 材料種類及其預處理 42
3.2.1 基板 42
3.2.2 基板清潔 42
3.2.3 鍍膜靶材 43
3.2.4 BGBM晶片 43
3.2.5 奈米燒結銀膏 44
3.3 濺鍍設備與鍍膜製程 44
3.3.1 四腔磁控式濺鍍系統 44
3.3.2 鍍膜製程 45
3.4真空熱壓設備 46
3.5 時效試驗設備 47
3.6 研磨 48
3.7 材料性質分析設備 49
3.7.1 掃描式電子顯微鏡(Scanning Electron Microscope,SEM) 49
3.7.2 能量色散光譜儀(EDX) 50
3.7.3 接合強度測試(Dage 4000 die shear test) 53
3.8 可靠度試驗(Reliability experiment) 55
3.8.1 高溫貯存試驗(High temperature storage test, HTS) 55
3.8.2 溫度循環測試(Temperature cycling test, TCT) 56
3.8.3 高溫水蒸汽壓力試驗 (Pressure Cook Test, PCT) 57

第四章 結果與討論 58
4.1 SLID接合Si/Ti/Ni/Ag/Sn晶片與DBC Cu/Ni/Pd/Au的反應機制 58
4.1.1 接合介面的介金屬化合物(IMC)分析 58
4.1.2 接合介面的接合強度分析 59
4.2 SLID接合Si/Ti/Ni/Ag/Sn晶片與DBC/Cu/Ni/Pd/Au的時效試驗 60
4.2.1 時效試驗後接合介面的接合強度分析與IMC分析 60
4.3 提高Si/Ti/Ni/Ag/Sn與DBC/Cu/Ni/Pd/Au SLID接合溫度試驗 63
4.3.1 提高接合溫度後接合介面的介金屬化合物(IMC)分析 63
4.3.2 提高接合溫度後接合介面的接合強度分析 65
4.4 提高Ti/Ni/Ag/Sn與DBC SLID接合溫度試驗的時效試驗 66
4.4.1 提高接合溫度的400℃/500小時時效試驗後接合強度分析 66
4.4.2 提高接合溫度的400℃/500小時時效試驗後介金屬化合物(IMC)分析 67
4.4.3 提高接合溫度的400℃/1000小時時效試驗後接合強度分析 69
4.4.4 提高接合溫度的400℃/1000小時時效試驗後介金屬化合物(IMC)分析 70
4.5 Ti/Ni/Ag/Sn與DBC SLID接合的可靠度試驗 72
4.5.1 高溫貯存試驗(High temperature storage test, HTS) 72
4.5.2 溫度循環測試(Temperature cycling test, TCT) 74
4.5.3 高溫水蒸汽壓力試驗 (Pressure Cook Test, PCT) 77
4.6 Ti/Ni/Sn與DBC、Ti/Ni/Ag/Sn與DBC SLID接合試驗 79
4.6.1 接合介面的接合強度分析 79
4.6.2 接合介面的介金屬化合物(IMC)分析 81
4.7 Ti/Ni/Cu/Sn與DBC、Ti/Ni/Cu/Ag/Sn與DBC SLID接合試驗 86
4.7.1 接合介面的接合強度分析 86
4.7.2 接合介面的介金屬化合物(IMC)分析 89
4.8 奈米銀燒結的固晶研究實驗 93
4.8.1 接合時間固定60mins、無壓,接合溫度分別250℃、300℃、350℃試驗 94
4.8.2 接合溫度與時間採取Gradient Profile方式、無壓與有施加接合壓力試驗 95
4.8.3 接合溫度與時間採取Gradient Profile方式,不同接合壓力0~40MPa試驗 97
4.8.4 燒結接合的時間增加對接合強度影響的試驗 98
4.8.5 試驗加入厚度30KÅ的Sn鍍層,Si/Ti/Ni/Ag/Sn整體厚度1、3、5、30KÅ,接合條件Gradient Profile方式,無施加壓力 99
4.8.6 DBC基板表面鍍層對奈米銀燒結強度的影響 100
4.8.7 試驗於奈米銀膏當中添加10%錫膏作為複合接合材料 101
4.9 研究結果小結 103

第五章 結論 108

參考文獻 110
個人簡介 116
-
dc.language.isozh_TW-
dc.subjectSLID接合zh_TW
dc.subjectBGBMzh_TW
dc.subject可靠度驗證zh_TW
dc.subject界面反應zh_TW
dc.subject奈米銀燒結zh_TW
dc.subjectSi/Ti/Ni/Ag/Snzh_TW
dc.subject介金屬化合物zh_TW
dc.subjectnano silver sinteringen
dc.subjectBGBMen
dc.subjectSLID bondingen
dc.subjectSi/Ti/Ni/Ag/Snen
dc.subjectinterfacial reactionen
dc.subjectintermetallic compounden
dc.subjectreliability verificationen
dc.title背晶金屬化矽晶片與DBC陶瓷基板固晶接合研究zh_TW
dc.titleStudy on Die Bonding of Backside Metallized Si Chip with DBC Ceramic Substratesen
dc.typeThesis-
dc.date.schoolyear111-1-
dc.description.degree博士-
dc.contributor.oralexamcommittee施漢章;徐治平;吳子嘉;張世穎;曹龍泉;林修任;劉乃瑋;王彰盟zh_TW
dc.contributor.oralexamcommitteeHan-Chang Shih;Jyh-Ping Hsu;Tzu-Chia Wu;Shih-Ying Chang;Lung-Chuan Tsao;Hsiu-Jen Lin;Nai-Wei Liu;Chang-Meng Wangen
dc.subject.keywordBGBM,SLID接合,Si/Ti/Ni/Ag/Sn,界面反應,介金屬化合物,可靠度驗證,奈米銀燒結,zh_TW
dc.subject.keywordBGBM,SLID bonding,Si/Ti/Ni/Ag/Sn,interfacial reaction,intermetallic compound,reliability verification,nano silver sintering,en
dc.relation.page121-
dc.identifier.doi10.6342/NTU202210181-
dc.rights.note同意授權(全球公開)-
dc.date.accepted2023-01-10-
dc.contributor.author-college工學院-
dc.contributor.author-dept材料科學與工程學系-
顯示於系所單位:材料科學與工程學系

文件中的檔案:
檔案 大小格式 
ntu-111-1.pdf5.99 MBAdobe PDF檢視/開啟
顯示文件簡單紀錄


系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。

社群連結
聯絡資訊
10617臺北市大安區羅斯福路四段1號
No.1 Sec.4, Roosevelt Rd., Taipei, Taiwan, R.O.C. 106
Tel: (02)33662353
Email: ntuetds@ntu.edu.tw
意見箱
相關連結
館藏目錄
國內圖書館整合查詢 MetaCat
臺大學術典藏 NTU Scholars
臺大圖書館數位典藏館
本站聲明
© NTU Library All Rights Reserved