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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃建璋(Jian-Jang Huang) | |
dc.contributor.author | Yu-Tzu Liao | en |
dc.contributor.author | 廖育資 | zh_TW |
dc.date.accessioned | 2023-03-19T23:41:22Z | - |
dc.date.copyright | 2022-09-06 | |
dc.date.issued | 2022 | |
dc.date.submitted | 2022-09-02 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/86191 | - |
dc.description.abstract | 隨著次世代 5G 通訊發展,對於元件操作頻率的需求逐漸增加,而三五族化合物半導體之電子元件擁有優異的高頻及直流特性,其中又以磷化銦(InP)之異質接面具有高電子遷移率、高功率密度與高臨界擊穿電場。相較於磷化銦高電子遷移率電晶體,磷化銦異質接面雙極性電晶體具有更高的崩潰電壓及更穩定的臨界電壓,許多研究透過調整其磊晶材料組成以及元件結構以提升元件之高頻特性。近期 研究指出基於磷化銦(InP)異質接面雙極性電晶體之功率增益截止頻率可以超過1 兆赫茲(THz)。 本研究針對磷化銦/砷化鎵銦/磷化銦(InP/InGaAs/InP)雙異質接面雙極性電晶體(DHBT)的磊晶結構、元件結構及製程步驟與相關參數進行開發與光罩設計,並設計窄線寬之射極金屬、自對準之基極金屬以及延伸至元件外部區域之基極電極以降低相關電阻及電容效應。磊晶結構設計方面,為了降低在基極-集極接面存在不連續的傳導帶之位能障蔽所造成的電流阻擋效應, 在基極-集極材料間加入漸變砷化鎵銦/砷化鋁銦之多層疊晶格結構,並且提高基極材料之摻雜濃度以降低接觸電阻。 為了確認及測試製程中相關參數以及條件,首先將使用尺度較大的 QAD 元件結構進行測試。透過傳輸線方法(TLM)量測金屬-半導體接觸情形,基極與集極金屬在蒸鍍後,以及射極金屬經過後,與半導體間形成歐姆接觸,接觸電阻率從3.22×10-6 Ω·cm2 到 10-4 Ω·cm2。在退火處理過後,集極接觸電阻率降低,但是基極與射極接觸電阻率隨之增加。 量測元件之射極-基極與基極-集極接面之電流與電壓關係圖,展現出二極體曲線,且從量測之嘉莫圖(Gummel plot)可推算最大電流增益為 5.28,在元件之共射極輸出特性曲線顯示偏移電壓約為 0.16 V。 透過 QAD 元件之製作,金屬-半導體介面之接觸特性以及乾、濕蝕刻使用之條件可應用於小尺度且窄線寬射極之雙異質接面雙極性電晶體之製程。為了減少電阻和電容對射頻特性的影響,利用電子束微影將射極區域縮小至 250 奈米,並利用側向蝕刻製造射極區域的底切,以達成自對準之基極金屬。基極金屬下方的基極與集極材料會被側向蝕刻,並且將基極電阻透過微米橋梁延伸至元件外以有效降低基極和集電極之間之寄生電容。透過掃描電子顯微鏡觀測元件之橫切面,射極金屬與上方用於量測之金屬間存在用於平坦化之光阻,導致在元件中流通的電子流極小,造成特性曲線上極小的電流增益。另外,在輸出特性曲線中的偏移電壓以及拐點電壓分別受到集極與射極面積之比例以及串聯電阻的影響,且串聯電阻可藉由射極-基極與基極-集極接面之二極體曲線推算。串聯電阻從 8.26 kΩ 至 90.40 kΩ會造成特性圖中 1.54 V 至 3.44 V 之拐點電壓。元件之崩潰電壓為 4.9 V。 為了提高平坦化過程中光阻 SU-8 之均勻性,避免光阻殘留在射極金屬用於量測之金屬間,應考慮加熱使光阻回流或是化學機械拋光之方法。再者,元件之射頻特性可以進一步提高藉由電子束微影製造小線寬之基極以及利用絕緣層製造表面鈍化的現象。 | zh_TW |
dc.description.abstract | In regards to the subsequent 5G (fifth generation) communications, the research in high-frequency applications for compound semiconductors have been developed more and more mature, where the high-profile electronics based on Indium Phosphide (InP) achieve maximum oscillation frequency exceeding 1 THz for Type-I InP/InGaAs and Type-II InP/GaAsSb heterojunction bipolar transistors (HBTs). This work addresses the design for the structure and epitaxial structure of double heterojunction InP/InGaAs/InP bipolar transistors (DHBT) to achieve high frequency characteristics, and develop the fabrication process and layout design for self-aligned InP HBT with narrow emitter metal and suspended μ-bridge connecting intrinsic base metal and base post. For the epitaxy, there are graded InGaAs/InAlAs chirped superlattice along with δ-doped layer at the base-collector junction to hinder current blocking effect, and the base layer is heavily doped to reduce contact resistivity. In order to examine the condition and parameters during fabrication, the quick-anddirty (QAD) structure is firstly brought into process. The metal-semiconductor contact characteristics are explored through the measurement of TLM patterns and the ohmic contact is presented for as-deposited base collector metal and emitter metal after thermal annealing with contact resistivity ranging from 3.22×10-6 Ω·cm2 to 3.68×10-4 Ω·cm2, and the contact resistivity for collector decreases after annealing process while the contact resistivity for the base and emitter metal increases. The QAD performs typical Gummel plot indicating the gain to be 5.28 with common emitter-base and base-collector diode curve, and the offset voltage of the characteristic curve is 0.16 V. With the metal composition and etching condition for QAD, several processes of HBT with narrow emitter can be ensured. To reduce the resistance and capacitance effect on the performance of RF characteristics, the emitter region will be narrowed down to 250 nm through the negative-tone resist for electron beam lithography, along with selfaligned base metal. The collector region beneath base metal would be aggressively laterally etched, and the application of micro-bridge to reduce the base pad area can effectively decrease the capacitance between base and collector. After planarization process, the HBT is cleaved through FIB and from the SEM images, there is SU-8 between the emitter metal and pad metal, leading to little electron current flowing through the HBT, and thus low current gain in the characteristic curve. The emitter with shorter length leads to higher ratio of collector area to emitter area, increasing offset voltage in the output characteristic curve. The high knee voltage for the HBTs is affected by the series resistance, extracted from the diode curve at both junctions, and higher series resistance, in range from 8.26 kΩ to 90.40 kΩ, results in higher knee voltage. To improve the uniformity of SU-8 during planarization process to avoid SU-8 left between emitter metal and pad metal, the reflow or the chemical mechanical polishing of the resist should be considered, and the RF performance can be further improved with sub-micrometer base metal fabricated through e-beam lithography, along with dielectric passivation on emitter, base, and collector semiconductors. | en |
dc.description.provenance | Made available in DSpace on 2023-03-19T23:41:22Z (GMT). No. of bitstreams: 1 U0001-0209202212172200.pdf: 6050379 bytes, checksum: 54ec356ebb29060938fe3ceace76270e (MD5) Previous issue date: 2022 | en |
dc.description.tableofcontents | 口試委員審定書 I 誌謝 II 中文摘要 III Abstract V Contents VII List of Figures X List of Tables XVI Chapter 1 Introduction 1 1.1 Background and Overview 1 1.2 Motivation and Purpose 2 1.3 Thesis Outline 3 Chapter 2 Theory and Literature Review 4 2.1 Material Properties 4 2.1.1 Physical Properties of InP 4 2.1.2 Physical Properties of InGaAs 7 2.2 Heterojunction Bipolar Transistor (HBT) 9 2.2.1 Structure 9 2.2.2 Operating Principle 11 2.2.3 Emitter 14 2.2.4 Base 16 2.2.5 Collector 18 2.2.6 Metal-Semiconductor Interface 20 2.3 DC Characteristics 24 2.3.1 Measurement of Transmission Line Model (TLM) 24 2.3.2 Regions of operation for HBT 26 2.4 Literature Review for Type-I InP HBT 29 Chapter 3 Device Fabrication and Measurement 36 3.1 Design of Epi Structure 36 3.2 Design of HBT Layout and Structure 37 3.2.1 Quick and Dirty (QAD) 38 3.2.2 Heterojunction Bipolar Transistor (HBT) 39 3.3 Process Flow of Device Fabrication 41 3.3.1 Quick and Dirty (QAD) 41 3.3.2 Heterojunction Bipolar Transistor (HBT) 42 3.4 Device Fabrication Methods 51 3.4.1 Electron Beam Lithography 51 3.4.2 Photolithography 52 3.4.3 Electron Beam Evaporation 53 3.4.4 Inductively Coupled Plasma – Reactive Ion Etching (ICP-RIE ) 54 3.4.5 Chemical Wet Etching 55 Chapter 4 Results and Discussion 57 4.1 QAD 57 4.1.1 TLM Measurement 57 4.1.2 DC Characteristics Analysis 60 4.2 HBT 64 4.2.1 TLM Measurement 66 4.2.2 DC Characteristics Analysis 68 Chapter 5 Conclusion and Prospect 71 5.1 Conclusion 71 5.2 Prospect 72 Reference 73 | |
dc.language.iso | en | |
dc.title | 磷化銦異質接面雙極性電晶體之製程開發與特性分析 | zh_TW |
dc.title | Fabrication and Characterization of Indium Phosphide (InP) Heterojunction Bipolar Transistors (HBTs) | en |
dc.type | Thesis | |
dc.date.schoolyear | 110-2 | |
dc.description.degree | 碩士 | |
dc.contributor.author-orcid | 0000-0002-5411-9678 | |
dc.contributor.oralexamcommittee | 吳育任(Yuh-Renn Wu),吳肇欣(Chao-Hsin Wu),林恭如(Gong-Ru Lin) | |
dc.subject.keyword | 磷化銦,雙異質接面雙極性電晶體,電子束微影,傳輸線方法,二極體曲線,嘉莫圖,輸出特性曲線, | zh_TW |
dc.subject.keyword | Indium Phosphide (InP),double heterojunction bipolar transistors (DHBT),e-beam lithography,μ-bridge,TLM analysis,diode curve,Gummel plot,output characteristic curve, | en |
dc.relation.page | 100 | |
dc.identifier.doi | 10.6342/NTU202203099 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2022-09-02 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 光電工程學研究所 | zh_TW |
dc.date.embargo-lift | 2022-09-06 | - |
顯示於系所單位: | 光電工程學研究所 |
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