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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳奕君(I-Chun Cheng) | |
dc.contributor.author | Chun-Wei Chang | en |
dc.contributor.author | 張鈞維 | zh_TW |
dc.date.accessioned | 2023-03-19T23:35:40Z | - |
dc.date.copyright | 2022-10-14 | |
dc.date.issued | 2022 | |
dc.date.submitted | 2022-09-28 | |
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R Rep., vol. 72, no. 6, pp.97-136, Jul. 2011, doi: 10.1016/j.mser.2010.12.001 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/86075 | - |
dc.description.abstract | 本研究主要探討可撓性鐵電電晶體在記憶體之應用。以金屬 / 鐵電材料 / 金屬 / 介電層 / 半導體( Metal - Ferroelectric - Metal - Insulator - Semiconductor, M - F - M - I - S )之結構於聚醯亞胺軟性基板( Polyimide, PI )製備鐵電電晶體( Ferroelectric Thin - Film Transistor, FeTFT ),由於PI基板其玻璃轉移溫度( Glass transition temperature, Tg )的限制,可耐受之製程溫度需控制約在400OC,故開發350OC低溫製程,並對鐵電層加入一介面層( Interface layer, IL )期望增加記憶窗口( Memory window, MW )。本研究使用Al2O3以及ZrO2兩種不同介面層,探討封裝前後對記憶窗口之影響,成功在加入介面層後使記憶窗口增加,在背通道裸露情況,其記憶窗口以ZrO2做為介面層之HZO鐵電層參數達4.3 V。待IGZO背通道經SiO2封裝後,去除外界水氣、氧氣等環境影響,並且由於300OC的封裝製程, 對於IGZO主動層以及鐵電層亦具有退火處理效果,使得三種鐵電層參數之記憶窗口皆有增加趨勢,尤其以Al2O3做為介面層之HZO鐵電層為最大,達5.8 V。除此之外,記憶窗口的增加實現多層式存儲操作( multilevle cell/code operation, MLC ),利用鐵電材料中電偶極部分翻轉特性,增加記憶密度,於multi - state VTH在無介面層及以ZrO2為介面層之鐵電電晶體達到2 bit;而以Al2O3做為介面層之鐵電電晶體則可達到3 bit。 | zh_TW |
dc.description.abstract | In this work, ferroelectric thin-film transistors ( Fe - TFTs ) with metal / ferroelectric / metal / insulator / semiconductor ( M - F - M - I - S ) structure are developed by monolithically integrating HfZrO2 ( HZO ) ferroelectric capacitors with amorphous indium-gallium-zinc oxide ( a-IGZO ) TFTs on Polyimide ( PI ) substrates. Since the PI substrate can withstand temperatures only up to ~400C, a low-temperature (350C ) process is developed for the Fe – TFTs. In addition, an interlayer is introduced to enlarge the memory window (MW). Al2O3 and ZrO2 are used as the interface layer here. The MW of back-channel exposed a-IGZO TFT with an ZrO2 interface layer, reaches 4.3 V. The MWs are enlarged after the back-channel is passivated by SiO2. In particular, the MW of the a-IGZO TFT with an Al2O3 interface layer achieves 5.8 V. This can be attributed to the protection of channel against the influence of moisture and oxygen and the annealing effect during the deposition of passivation layer at 300C. The large MW can enable multilevel cell/code operation ( MLC ). The partial flipping of ferroelectric dipoles can be applied to high-density memory applications. Finally, 2 - bit operation is demonstrated in the Fe-TFT without the interface layer or with a ZrO2 interface layer, and 3 - bit operation is achieved in the Fe - TFT with an Al2O3 interface layer. | en |
dc.description.provenance | Made available in DSpace on 2023-03-19T23:35:40Z (GMT). No. of bitstreams: 1 U0001-2609202213345500.pdf: 7467969 bytes, checksum: 1e43ea8ce803619e9bf27ef17988eabf (MD5) Previous issue date: 2022 | en |
dc.description.tableofcontents | 誌謝 I 摘要 II Abstract III 目錄 IV 圖目錄 VIII 表目錄 XIV 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機與目的 3 1.3 論文架構 5 第二章 理論基礎與文獻回顧 7 2.1 薄膜電晶體簡介 7 2.1.1 薄膜電晶體之元件結構 7 2.1.2 薄膜電晶體之工作原理 9 2.1.3 薄膜電晶體之介電層電性分析 10 2.1.4 薄膜電晶體之特徵參數 11 2.2 鈍化層對於氧化銦鎵鋅薄膜電晶體之影響 15 2.3 氧化鉿基之鐵電特性 17 2.3.1 氧化鉿基之鐵電材料 17 2.3.2 退火處理對HZO之鐵電性形成機制 17 2.3.3 鐵電電容其上下電極材料對HZO薄膜之影響 21 2.4 氧化物半導體作為通道之HZO鐵電電晶體式記憶體 25 2.4.1 鐵電電晶體式記憶體 25 2.4.2 M - F - I - S結構之鐵電電晶體式記憶體 27 2.4.3 M - F - M - I - S之鐵電電晶體式記憶體 30 2.4.4 溫度之於鐵電電電晶體之電性表現 33 2.5 低溫製程下之可撓性鐵電電晶體 36 2.5.1 有機鐵電材料 36 2.5.2 氧化鉿鋯鐵電材料 39 2.6 Interface layer對於鐵電電晶體之影響 43 第三章 實驗方法與步驟 47 3.1 薄膜沉積方法 47 3.1.1 電子束蒸鍍系統 47 3.1.2 射頻磁控濺鍍系統 48 3.1.3 原子層沉積系統 49 3.1.4 電漿輔助化學氣相沉積系統 50 3.1.5 X光繞射分析儀 52 3.2 黃光微影製程 53 3.3 蝕刻製程 55 3.3.1 濕式蝕刻製程 55 3.3.2 乾式蝕刻製程 56 3.4 金屬 / 介電層 / 金屬( M - I - M )電容製備流程 58 3.5 GIXRD量測分析鐵電層薄膜製備流程 60 3.6 鐵電電容串聯IGZO TFT之製備流程 61 3.6.1 鐵電電容串聯IGZO TFT之尺寸介紹 61 3.6.2 PI軟性基板、鐵電電容與IGZO TFT製作流程 63 3.7 量測分析 71 3.7.1 電容-電壓(C-V)量測方法 71 3.7.2 M - F - M鐵電電容P - V Curve量測方法 72 3.7.3 IGZO薄膜電晶體量測方法 73 3.7.4 鐵電電容串聯IGZO TFT量測方法 74 3.7.5 鐵電電晶體之Multilevel of Endurance量測方法 75 3.7.6 鐵電電容串聯IGZO TFT之Multi - state of VTH 量測方法 76 第四章 結果與討論 77 4.1 鐵電電容特性分析 77 4.1.1 鐵電層之晶相特性分析 77 4.1.2 鐵電層之C-V特性分析 80 4.1.3 鐵電層之P-V特性分析 82 4.2 IGZO TFT元件特性分析 84 4.2.1 介電層之C-V特性分析 84 4.2.2 IGZO TFT 背通道裸露與封裝SiO2電性分析 85 4.3 鐵電電晶體封裝前後之特性分析 90 4.3.1 背通道層裸露之鐵電電晶體特性 91 4.3.2 封裝後鐵電電晶體之特性 104 4.4 鐵電電晶體之記憶效應 119 4.5 鐵電電晶體之Multi-state of VTH 分析[63] 123 4.6 鐵電電晶體之Endurance分析 128 4.6.1 短Pulse Width之Stress的Multilevel of Endurance量測 128 4.6.2 長Pulse Width之Stress的Multilevel of Endurance量測 130 第五章 結論 134 5.1 結論 134 5.2 未來展望 136 A. 附錄 138 I.以GIXRD分析金屬應力對鐵電層結晶之影響 138 II.ZrO2之C - V特性量測 140 III.可撓性電性量測分析 141 參考文獻 147 | |
dc.language.iso | zh-TW | |
dc.title | 以氧化銦鎵鋅作為通道層之可撓性氧化鉿鋯鐵電薄膜電晶體之研究 | zh_TW |
dc.title | Flexible HfZrO2 Ferroelectric Thin-Film Transistors Based on InGaZnO Channels | en |
dc.type | Thesis | |
dc.date.schoolyear | 110-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳建彰(Jian-Zhang Chen),李敏鴻(Min-Hung Lee) | |
dc.subject.keyword | M - F - M - I - S,可撓性基板,鐵電薄膜電晶體,氧化鉿鋯,氧化銦鎵鋅,介面層Al2O3 & ZrO2,多層式存儲, | zh_TW |
dc.subject.keyword | M - F - M - I - S,Flexible substrate,Fe - TFT,HZO,IGZO,Interface layer Al2O3 & ZrO2,Multilevel cell/code operation, | en |
dc.relation.page | 154 | |
dc.identifier.doi | 10.6342/NTU202204083 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2022-09-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 光電工程學研究所 | zh_TW |
dc.date.embargo-lift | 2024-09-28 | - |
顯示於系所單位: | 光電工程學研究所 |
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