使用數位控制可變增益放大器之4位元Ka頻段主動向量和式相移器

Abstract

本論文提出一操作於 Ka 頻帶之數位控制主動式向量合成器(vector sum phase shifter, VSPS)，相移器主要操作於Ka頻段，目的為應用於5G無線通訊系統(5th generation wireless system)的波束成型技術。 本論文之相移器使用相位可反相可調衰減器(phase-invertible variable attenuator, PIVA)及90°正交耦合器來產生正交(in-phase and quadrature , IQ)訊號，將產生的正交訊號透過可變增益放大器(variable gain amplifier)調整訊號的振幅，最後透過功率合成器產生需要的相位，其中使用電流式數位類比轉換器(current DAC)控制可變增益放大器，並使用解碼器控制電流式數位類比轉換器以減少佈局時的PAD數量。使用到的數位訊號包含解碼器、衰減器輸入、PIVA控制四相位輸入，總共8個數位訊號實現4位元的相移器。 本論文將呈現兩顆晶片，在模擬設計階段，其中一顆為七種狀態的數位控制可變增益放大器，在28GHz時其增益範圍為14dB， 且在狀態切換時的相位變化小於10°。第二顆為數位控制4位元主動向量和式相移器，在28GHz時16種相移狀態平均增益為4.65dB，均方根相位誤差小於3.5°、均方根增益誤差小於0.8dB，直流功耗約為30mW。 此論文電路均採用台積電0.18μm CMOS製程實現，兩顆晶片皆因佈局因素與模擬出現誤差，且於論文中除錯完成。第一顆晶片數位控制可變增益放大器中心頻為21GHz，最大增益為-1.49dB，增益範圍約為25dB。第二顆晶片主動向量和式相移器中的可變增益放大器也頻偏至21GHz，但相移器在28GHz時仍具相移功能，最大增益為-29.84dB，其均方根相位誤差約為5.9°、均方根增益誤差約為0.85dB，且直流功耗約為29mW。

This thesis proposes a digital vector sum phase shifter (VSPS) operating at Ka-band. This work is designed for the beam-forming in 5th generation wireless system. The phase shifter in this thesis uses a phase-invertible variable attenuator (PIVA) and 90°coupler to achieve in-phase and quadrature (I/Q) signals then, uses variable gain amplifier (VGA) to adjust the amplitude of I/Q signals, and finally combines I/Q signals by power combiner to generates the required phase. A current DAC is used to control the variable gain amplifier, and a decoder is used to control this current DAC to reduce the number of pads in chip layout. The digital signals used include decoder, attenuator in variable gain amplifier, PIVA control for four phase, total of 8 digital signals to realize a 4-bit VSPS. This thesis will present two chips, the first chip is a digitally controlled variable gain amplifier with seven gain states. Its gain range is 14dB, and the phase variation among gain state switching is less than 10°.The second chip is a digitally controlled 4-bit vector sum phase shifter. The average gain of 16 states in simulation is 4.65dB, the RMS phase error is less than 3.5°, RMS gain error is less than 0.8dB at 28GHz. DC power consumption is 30mW. The circuits in this thesis are all implemented by TSMC’s 180nm CMOS process. These two chips have errors in layout, and these errors are debugged in the thesis. The center frequency of the first chip is shifted to 21GHz in measurement, and its gain range is about 25dB with maximum gain at -1.49dB. The center frequency of digitally controlled VGA in second chip also shifted to 21GHz, but the phase shifter still works at 28GHz. Its maximum gain is -29.84dB at 28GHz with RMS phase error at 5.9°, RMS amplitude error at 0.85dB, and DC power consumption is about 29mW.