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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃定洧 | zh_TW |
dc.contributor.advisor | Ding-Wei Huang | en |
dc.contributor.author | 施元丁 | zh_TW |
dc.contributor.author | Yuan-Ting Shih | en |
dc.date.accessioned | 2023-03-19T23:27:42Z | - |
dc.date.available | 2023-11-10 | - |
dc.date.copyright | 2022-10-20 | - |
dc.date.issued | 2022 | - |
dc.date.submitted | 2002-01-01 | - |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/85886 | - |
dc.description.abstract | 為了簡化製程及降低製造成本,我們設計一種用於覆矽絕緣層 (SOI) 奈米光子波導之0.22 µm厚的單層部分拋物線型交錯結構 (PPSLC),其下氧化矽層厚度為2 µm,元件總面積為6 µm × 6 µm,PPSLC每臂具有3 µm長的單層部分拋物線型結構,輸入1.55 µm波長的基模入射光,藉由調整並優化其輸出入及交錯區域附近結構的幾何曲線,實現了97.90% 的高傳輸率 (−0.092 dB) 和 −62 dB的低串擾。相較於雙層拋物線型交錯結構(DLPTC),PPSLC的單層結構不僅能簡化製程及降低成本、縮小交錯結構元件尺寸利於生產更密集的矽光子元件及電路,且即使在±10 nm的製造尺寸誤差下也能保持96.90% 以上的高傳輸率。我們更在PPSLC 上設計橋接次波長光柵 (BSWG) 波導和對角週期性孔洞 (DPHs) 結構,進一步提高傳輸率,BSWG 位於PPSLC的輸出入端外側,DPHs 位於PPSLC的交錯區域中。相較於PPSLC,其元件總面積 (6.2 µm × 6.2 µm) 僅增加6.78%,而傳輸率提高至98.72% (−0.056 dB),串擾降低至−65 dB。本論文的設計方法不但適用於製造更低成本及更高傳輸率的交錯結構,更可應用於矽光子積體電路的其他元件的設計。 | zh_TW |
dc.description.abstract | To simply fabrication processes and reduce cost, we design a new waveguide crossing — a partial parabolic single layer crossing (PPSLC), which has 0.5-µm-wide input/output waveguides and occupies a footprint of 6 µm × 6 µm upon a silicon-on-insulator (SOI) wafer with 0.22-µm-thick silicon device layer on 2-μm buried oxide. Each PPSLC arm has a 3-µm partial parabolic structure, which is modified and optimized by crossing curves around the crossing regions and input/output regions of waveguide crossing to fit the input initial status of the fundamental mode light. The optimization results of PPSLC shows good performances of 97.90% high transmission (−0.092 dB) and −62 dB low crosstalk at an input wavelength of 1.55 µm. Compared with the double layer parabolic taper crossing (DLPTC), PPSLC not only simplifies the fabrication processes, reduces cost, and shrinks the dimension size to contribute more space for compact photonic circuits on a die, but also keeps transmission high than 96.90% even below ±10 nm fabrication dimension errors. Moreover, we create composite subwavelength structures, including bridged subwavelength grating (BSWG) waveguide structures and diagonally periodic holes (DPHs), on a PPSLC to enhance its transmission. The BSWG is located around the entrance/exit of the input/output regions of the PPSLC and the DPHs are set in the crossing region of the PPSLC. The footprint of the kind of PPSLC with BSWG and DPHs is 6.2 µm × 6.2 µm. We gain optimized results of improving the transmission up to 98.72% (−0.056 dB) and the crosstalk as low as −65 dB. This design can be applied for producing waveguide crossings or other parts of photonic integrated circuits to contribute to their development. | en |
dc.description.provenance | Made available in DSpace on 2023-03-19T23:27:42Z (GMT). No. of bitstreams: 1 U0001-2809202215205300.pdf: 6027046 bytes, checksum: 4246246cdbd5a107dca24f8e4076a3d2 (MD5) Previous issue date: 2022 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii ABSTRACT iv CONTENTS v LIST OF FIGURES viii LIST OF TABLES xi Chapter 1 Introduction 1 1.1 Photonic Integrated Circuits (PICs) 1 1.2 Waveguide Crossings 3 1.3 Double Layer Parabolic Taper Crossing (DLPTC) 6 1.4 Research Motivation and Structure of Dissertation 7 Chapter 2 Theoretical Background 9 2.1 Planar Optical Waveguides 9 2.1.1 Introduction 9 2.1.2 Radiation Field from Optical Waveguide Discontinuity 9 2.1.3 Radiation Pattern of Gaussian Beam 11 2.2 Finite-Difference Time-Domain (FDTD) Method 14 2.2.1 Introduction 14 2.2.2 Boundary Condition − Perfectly Matched Layer (PML) 18 2.3 Particle Swarm Optimization (PSO) 19 2.3.1 Introduction 19 2.3.2 Algorithm of PSO 21 2.3.3 Strategy of Adaptive Optimization for Global Extrema 23 2.4 Subwavelength Grating (SWG) Structures 25 2.4.1 Introduction 25 2.4.2 Subwavelength Grating (SWG) Waveguide 25 2.4.3 Bridged Subwavelength Grating (BSWG) Waveguide 26 Chapter 3 Design and Simulation Results of Modified DLPTC 28 3.1 DLPTC modified with Crossing Curves around Lower Crossing Regions 28 3.1.1 Segmentation Levels of Lower Crossing Regions 29 3.1.2 Flow Chart of Optimization Processes 30 3.1.3 Optimization Results 31 3.2 DLPTC modified with Crossing Curves around Upper and Lower Crossing Regions 32 3.2.1 Segmentation Levels of Upper Crossing Regions 33 3.2.2 Optimization Results 34 3.2.3 Comparing Optimization Results with DLPTC 36 Chapter 4 Design and Simulation Results of Partial Parabolic Single Layer Crossing (PPSLC) 38 4.1 Design 38 4.2 Mathematical Model 39 4.3 Segmentation positions of PPSLC 41 4.4 Optimization Results of PPSLC 42 4.5 Comparisons of Crossings Areas (Footprints) 46 4.6 Dimension Tolerance 48 Chapter 5 Improving Transmission for PPSLC with Composite Subwavelength Structures 50 5.1 Introduction 50 5.2 Tapered BSWG 51 5.3 DPHs 56 5.4 PPSLC with Tapered BSWG and DPHs 58 5.4.1 Design 58 5.4.2 Optimization Results 58 5.4.3 Dimension Tolerance 62 5.4.4 Comparison of Crossing Designs with Similar Minimum Dimension 64 Chapter 6 Conclusion 65 6.1 Performance Comparison of Crossings 65 6.2 Summary 66 REFERENCES 67 Curriculum Vitae 81 Appendix 1 (Publication 1) 82 Appendix 2 (Publication 2) 83 | - |
dc.language.iso | zh_TW | - |
dc.title | 用於覆矽絕緣層奈米光子波導之單層部分拋物線型交錯結構設計 | zh_TW |
dc.title | Design of Partial Parabolic Single Layer Crossing for Silicon-on-Insulator Nanophotonic Waveguides | en |
dc.type | Thesis | - |
dc.date.schoolyear | 110-2 | - |
dc.description.degree | 博士 | - |
dc.contributor.author-orcid | 0000-2224-6580-3838 | |
dc.contributor.oralexamcommittee | 江海邦;蕭惠心;張祐嘉;張書維 | zh_TW |
dc.contributor.oralexamcommittee | Hai-Pang Chiang;Hui-Hsin Hsiao;You-Chia Chang;Shu-Wei Chang | en |
dc.subject.keyword | 積體奈米光子,波導元件,次波長光柵,橋接次波長光柵, | zh_TW |
dc.subject.keyword | Integrated nanophotonic,Waveguide devices,Subwavelength grating,SWG,Bridged subwavelength grating,BSW, | en |
dc.relation.page | 87 | - |
dc.identifier.doi | 10.6342/NTU202204202 | - |
dc.rights.note | 同意授權(全球公開) | - |
dc.date.accepted | 2022-09-29 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 光電工程學研究所 | - |
dc.date.embargo-lift | 2022-10-20 | - |
顯示於系所單位: | 光電工程學研究所 |
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