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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 王暉(Huei Wang) | |
dc.contributor.author | Ziu-Hao Wang | en |
dc.contributor.author | 王子豪 | zh_TW |
dc.date.accessioned | 2021-05-20T00:57:06Z | - |
dc.date.available | 2021-02-22 | |
dc.date.available | 2021-05-20T00:57:06Z | - |
dc.date.copyright | 2021-02-22 | |
dc.date.issued | 2021 | |
dc.date.submitted | 2021-02-02 | |
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Wang, 'A high linearity 24-GHz down-conversion mixer using distributed derivative superposition technique in 0.18-m CMOS Process,' IEEE Microwave and Wireless Components Letters, vol. 28, no. 1, pp. 49-51, Jan. 2018. [32] Z. Jiang, B. Lu, Y. Wang and H. Wang, 'A compact 38-54 GHz sub-harmonic mixer with improved linearity in 65-nm CMOS,' IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Nanjing, China, 2019. [33] H. Li and C. E. Saavedra, 'Linearization of active downconversion mixers at the IF using feedforward cancellation,' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 4, pp. 1620-1631, April 2019. [34] M. Mollaalipour and H. Miar-Naimi, 'Design and analysis of a highly efficient linearized CMOS subharmonic mixer for zero and low-IF Applications,' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2275-2285, June 2016. [35] M. Mollaalipour and H. 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Wang, 'A 40-GHz high Linearity transmitter in 65-nm CMOS technology with 32-dBm OIP3,' IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, USA, 2019. [40] J. Y. Su, S. C. Tseng, C. Meng, P. Y. Wu, Y. T. Lee, and G. W. Huang,“Ka/Ku-Band pHEMT gilbert mixers with polyphase and coupled-line quadrature generators,” IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 5, pp. 1063-1073, May 2009,. [41] J. Li and Q. J. Gu, 'Harmonic-based nonlinearity factorization of switching behavior in up-conversion mixers,' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 7, pp. 2468-2477, July 2019. [42] Z. -H. Wang, C. -N. Chen and H. Wang, 'A 30-40 GHz Continuous Class F−1 Power Amplifier with 35.8% Peak PAE in 65 nm CMOS Technology,' 2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Hiroshima, Japan, 2020. [43] Z. Wang, C. Cheng, T. Huang and H. Wang, 'A 28-GHz High Linearity Up-conversion Mixer Using Second-Harmonic Injection Technique in 28-nm CMOS Technology,' in IEEE Microwave and Wireless Components Letters, 2021. [44] X. Xu et al., 'A 21-39.5 GHz power amplifier for 5G wireless systems in 22 nm FD-SOI CMOS,' 2019 IEEE Asia-Pacific Microwave Conference (APMC), Singapore, Singapore, 2019. [45] D. Wang, W. Chen, L. Chen, X. Liu and Z. Feng, 'A Ka-Band highly linear power amplifier with a linearization bias circuit,' 2019 IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, USA, 2019. [46] F. Wang, T. Li and H. Wang, '4.8 A highly linear super-resolution mixed-signal Doherty power amplifier for high-efficiency mm-Wave 5G multi-Gb/s communications,' 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019. [47] S. N. Ali, P. Agarwal, S. Gopal and D. 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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8544 | - |
dc.description.abstract | 本論文包含兩個部分都是希望運用在第五代行動通訊系統中。第一部分應用在30到40 GHz寬頻連續反F類功率放大器,使用65奈米金氧半場電晶體製程設計。第二部分是應用於28 GHz高線性度升頻器,使用28米金氧半場電晶體製程設計。 論文中首先提出了一個應用在30到40 GHz連續模式反F(CCF-1)功率放大器設計以同時達到寬頻且高效率的表現。此電路為了實現連續反F操作,利用輸出變壓器並且在其中加入電容用來實現理想基頻與諧波阻抗設計。我們可以透過這種方式設計來減少匹配電路的設計複雜度與損耗,除此之外,在本章當中也討論放大器的線性度且電路的AM/PM失真因為輸出諧波匹配而有一定程度的改善。量測結果顯示本文提出的功率放大器在34 GHz有17.9 dBm的飽和輸出功率且大訊號頻寬包含從30到40 GHz,在此輸出功率下仍有35.8%功率附加效益,還得到15 dBm輸出功率的增益1dB壓縮點。在調變量測使用64-QAM的訊號下,此電路達到400MHz調變頻寬且有9.2 dBm的平均輸出功率和12.5 %平均功率附加效率,且錯誤向量大小(EVM)小於-28 dB。 另外提出一個在轉導級使用二階交互調變注入技術達到高線性度的升頻器,因此透過混和低頻輸入訊號和二階交互調變訊號可以在轉導級產生一個正的三階交互調變訊號,並且透過電晶體操作在三級區來放大此訊號,最後本電路展現出在寬輸入功率範圍下都有三階交互調變功率抑制。量測結果顯示此升頻器有-6.4 dB的轉換增益與-2.2 dBm輸出功率的增益1dB壓縮點,直流功率損耗為19 mW,而雙頻量測(two-tone measurement)則顯示明顯的三階交互調變功率抑制且輸出三階截點功率為10.2 dBm。除此之外,在調變訊號量測使用256-QAM的訊號下,此電路展現出在有三階交互調變失真抑制下輸出功率可以改善。 | zh_TW |
dc.description.abstract | This thesis is composed of two parts and both of them aim for the fifth-generation wireless communication. The first part is a 30-40 GHz broadband power amplifier with continuous Class-F-1 matching fabricated in 65-nm CMOS process. The other exhibits a 28-GHz high linearity up-conversion mixer fabricated in 28-nm CMOS process. At first, a 30-40 GHz continuous-mode inverse Class-F (Class-F-1) power amplifier design to achieve both high efficiency and wide bandwidth is presented. The proposed fundamental and harmonic matching are achieved using the output transformer with an embedded capacitor for continuous inverse class-F operation. In this way, we can reduce the harmonic load complexity and insertion loss significantly. Moreover, linearity of the power amplifier is discussed and the improvement of AM-PM distortion due to harmonic output matching is also exhibited. Therefore, the proposed continuous Class-F-1 PA shows a saturated output power (Psat) of 17.9 dBm, output power bandwidth (30 to 40 GHz) with 35.8 % peak PAE, and output 1-dB compression point (OP1dB) of 15.0 dBm at 34 GHz. When tested with a single-carrier 64-QAM signal, this PA achieves bandwidth of 400 MHz, 9.2-dBm average output power, and 12.5% average PAE under error vector magnitude (EVM) -28 dB. The other part is a high linearity up-conversion mixer with a second-order intermodulation (IM2) signal injection technique adopted in the transconductance stage. So, the positive third-order intermodulation (IM3) signal is generated from mixing the IM2 signal and IF input signal with transistors biasing in triode region. The proposed mixer achieves the IM3 power improvement of 10 dB in a wide IF power range with the proposed technique. The measurement results demonstrate a conversion gain of -6.4 dB and output 1-dB compression point (OP1dB) of -2.2 dBm with 19 mW. The two-tone measurement results exhibit a conspicuous improvement of IM3 and achieves 10.2 dBm output third-order intercept point (OIP3). Furthermore, with the modulation measured results using single-carrier 256-QAM signal, the proposed mixer also exhibits an output power level enhancement of 3 dB when the linearizer turns on. | en |
dc.description.provenance | Made available in DSpace on 2021-05-20T00:57:06Z (GMT). No. of bitstreams: 1 U0001-2601202114104500.pdf: 12994267 bytes, checksum: 1c3e7bc8f7caec183af67eed666b481a (MD5) Previous issue date: 2021 | en |
dc.description.tableofcontents | 口試委員會審定書 # 誌謝 ii 中文摘要 iv ABSTRACT vi CONTENTS viii LIST OF FIGURES xii LIST OF TABLES xx Chapter 1 Introduction 1 1.1 Backgrounds and Motivations 1 1.2 Literature Survey 3 1.2.1 Broadband and High Efficiency Power Amplifier 3 1.2.2 High Linearity Up-Conversion Mixer 5 1.3 Contributions 7 1.3.1 30-40 GHz Broadband and Efficiency CMOS PA 7 1.3.2 28-GHz CMOS up-conversion mixer 8 1.4 Thesis Organization 9 Chapter 2 A 30-40 GHz Power Amplifier with Continuous Class F-1 matching in 65 nm CMOS Technology 11 2.1 Introduction 11 2.2 Circuit Design 15 2.2.1 Circuit Architecture 16 2.2.2 Device and Bias selection 17 2.2.3 Capacitance-Based Neutralization 24 2.2.4 Load-pull Simulation for Continuous Class-F-1 operation 27 2.2.5 Design of the Matching Networks 30 2.2.6 Simulation Results 37 2.2.7 Stability Check of the Circuit 44 2.3 Experimental Results 47 2.3.1 DC Operating Point 47 2.3.2 S-Parameters and Large Signal Power Sweep Measurement 48 2.3.3 Digital Modulation 52 2.4 Summary 60 Chapter 3 A 28 GHz High Linearity Up-conversion Mixer Using Second-Harmonic Injection Technique in 28 nm CMOS Technology 64 3.1 Introduction 64 3.2 Circuit Design 69 3.2.1 High Linearity Up-Conversion Mixer 69 3.2.2 The Design of the Active Mixer Core 70 3.2.3 The Design of transconductance stage and IM2 signal injection technique 80 3.2.4 Simulation Results 87 3.3 Experimental Results 92 3.3.1 Large-signal CW Performances 92 3.3.2 Digital Modulation 102 3.3.3 The Linearity Consideration of the Up-conversion mixer 107 3.4 Summary 111 Chapter 4 Conclusions 113 REFERENCE 115 | |
dc.language.iso | en | |
dc.title | 應用於第五代行動通訊之功率放大器與混頻器的研究 | zh_TW |
dc.title | Research of Power Amplifier and Up-Conversion Mixer for 5G Mobile Communications | en |
dc.type | Thesis | |
dc.date.schoolyear | 109-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃天偉(Tian-Wei Huang),林坤佑(Kun-You Lin),蔡作敏(Tsai Zuo-Min),章朝盛(Chau-Ching Chiong) | |
dc.subject.keyword | 第五代行動通訊,互補式金屬氧化物半導體製程,升頻器,功率放大器,Ka頻段, | zh_TW |
dc.subject.keyword | 5G,CMOS,Power amplifier,Mixer, | en |
dc.relation.page | 121 | |
dc.identifier.doi | 10.6342/NTU202100179 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2021-02-03 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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