一個有時間偏移校正之十二位元每秒十億次取樣的時間交錯式連續漸進式類比至數位轉換器

Abstract

Software-defined radar systems需要十億赫茲高取樣頻率的ADC 作為前端。連續寄進式(SAR) ADC在現代CMOS製程中具有很好的電能效率，因此適用於雷達系統的前端。 本作品文提出了一個在有時間偏移校正之十二位元每秒十億次取樣的時間交錯式連續漸進式類比至數位轉換器，實現於 TSMC 28nm CMOS，由一個 6-bit Coarse ADC 組成，並輔助四個 12-bit Fine ADC 實現高速、高解析度和低功耗。此外，時序偏移校準消除了通道之間的偏移效應。用於時序偏移校正，它與Subranging SAR ADC架構相結合，無需額外的參考通道。 本論文所提出的架構有兩個主要問題。第一個是穩壓非線性，第二個是Subranging SAR內部的頻寬不匹配。根據以前的量測經驗，穩壓非線性被低估，並限制了取樣頻率。Subranging SAR內部的頻寬不匹配會導致取樣誤差並限制輸入頻率。 電容製程不匹配和C-DAC穩壓非線性之間需要取捨。電容製程不匹配很難在模擬中驗證。儘管在R+C+CC模擬中可以觀察到C-DAC穩壓非線性；但是從之前的測量經驗來看我們低估了此效應。 本作品旨在通過兩種類型的 C-DAC 佈局來驗證電容製程不匹配和 C-DAC 穩壓非線性。第一個 TI SAR 使用具有高速穩壓的 C-DAC 佈局，具有較大的電容製程不匹配，第二個 TI SAR 使用具有穩壓非線性 C-DAC 佈局，並有較少的電容製程不匹配。 First TI SAR ADC的單通道測量結果在Fs=850MS/s與Fin=500kHz輸入頻率信號下，SNDR達到了51.54db，四通道測量結果達到了41. 31db。Secoond TI SAR ADC具有較好的電容匹配，但穩壓非線性較差。Secoond TI SAR ADC 的單通道量測結果在Fs=350MS/s與Fin=50kHz下，SNDR達到了 60.04 db而四通道測量達到了55.84db。

Software-defined radar systems require the Gigahertz high sampling rate ADC as the front-end. Successive approximation-register (SAR) ADC is power efficient in the modern CMOS process, hence is suitable for the front-end of the radar system. This thesis proposed a 12-b 1-GS/s TI SAR ADC with Timing Skew calibration in 28nm CMOS, which consists of a 6-bit Coarse ADC to assist the four 12-bit Fine ADC in achieving high speed, high resolution, and low power. Besides, a Timing Skew calibration eliminates the skew effect between the channels. The Zero-Crossing algorithm is used in Timing Skew calibration, and it is combined with the Subranging architecture to eliminate the need for an additional reference channel. There is a trade-off between the capacitor process mismatch and C-DAC settling nonlinearity. Capacitor process mismatch is hard to verify in simulation. C-DAC settling nonlinearity can be observed in R+C+CC simulation; however, it is under-estimated. There are two significant problems with the proposed architecture. The first is the settling nonlinearity, and the second is the Subranging bandwidth mismatch. Settling nonlinearity is underestimated from the previous measurement experience, which limits the sampling rate. The Subranging bandwidth mismatch causes the sampling error and limits the input frequency. The proposed work aims at verified the capacitor process mismatch and C-DAC settling nonlinearity by two types of C-DAC layout. The First TI SAR uses the C-DAC layout with good settling linearity with large capacitor process mismatch, and the Second TI SAR uses the C-DAC layout with poor settling linearity with less capacitor process mismatch. The single-channel measurement result of the First TI SAR ADC achieves SNDR 51.54db at the conversion of 850MS/s with a 500kHz input signal, and the four-channel measurement result achieves SNDR 41.31db. The Second TI SAR ADC has better capacitor matching with the poor settling nonlinearity. At the conversion of 350MS/s with a 50kHz input signal, the single-channel measurement result of the Second TI SAR ADC achieves an SNDR of 60.04 db, and the four-channel measurement result of TI SAR ADC achieves an SNDR of 55.84db.