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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang | jlhuang@ntu.edu.tw | ), | |
dc.contributor.author | Chi-Jhe Li | en |
dc.contributor.author | 李其哲 | zh_TW |
dc.date.accessioned | 2023-03-19T22:18:01Z | - |
dc.date.copyright | 2022-09-19 | |
dc.date.issued | 2022 | |
dc.date.submitted | 2022-09-16 | |
dc.identifier.citation | K.-H. Chen, B.-Y. Yang, J.-R. Liang, H.-L. Chen, and J.-L. Huang, “Automatic test program generation for transition delay faults in pipelined processors,” in 2021 IEEE International Test Conference in Asia (ITC-Asia), pp. 1–6, 2021. H.-L. Chen, “Case Study: Test Program Generation of RISC-V Processor for Software-Based Self-Test,” Master’s thesis, National Taiwan University, 2021. E. Weglarz, K. Saluja, and T. Mak, “Testing of hard faults in simultaneous multithreaded processors,” in Proceedings. 10th IEEE International On-Line Testing Symposium, pp. 95–100, 2004. M. Psarakis, D. Gizopoulos, E. Sanchez, and M. Sonza Reorda, “Microprocessor software-based self-testing,” IEEE Design Test of Computers, vol. 27, no. 3, pp. 4–19, 2010. K. Kambe, M. Inoue, and H. Fujiwara, “Efficient template generation for instructionbased self-test of processor cores,” in 13th Asian Test Symposium, pp. 152–157, 2004. M. Nakazato, S. Ohtake, M. Inoue, and H. Fujiwara, “Design for testability of software-based self-test for processors,” in 2006 15th Asian Test Symposium, pp. 375–380, 2006. V. Singh, M. Inoue, K. K. Saluja, and H. Fujiwara, “Instruction-based self-testing of delay faults in pipelined processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 11, pp. 1203–1215, 2006. Y. Zhang, H. Li, and X. Li, “Automatic test program generation using executingtrace- based constraint extraction for embedded processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 7, pp. 1220–1233, 2013. N. Kranitis, A. Paschalis, D. Gizopoulos, and G. Xenoulis, “Software-based selftesting of embedded processors,” IEEE Transactions on Computers, vol. 54, no. 4, pp. 461–475, 2005. M. Psarakis, D. Gizopoulos, M. Hatzimihail, A. Paschalis, A. Raghunathan, and S. Ravi, “Systematic software-based self-test for pipelined processors,” in 2006 43rd ACM/IEEE Design Automation Conference, pp. 393–398, 2006. N. Hage, R. Gulve, M. Fujita, and V. Singh, “On testing of superscalar processors in functional mode for delay faults,” in 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), pp. 397–402, 2017. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84623 | - |
dc.description.abstract | 由於汽車電子和醫療電子產品的快速發展帶來的系統可靠性問題,軟體自我測試(Software-based self-test, SBST)受到更多關注。 在之前的研究[1]中,提出了一種基於模組無關的(module-independent)測試程式樣板(template)和受約束的自動測試型樣產生系統(constrained automatic test pattern generation)的轉換方法,將全掃描測試型樣(full-scan test pattern)轉換為測試程式。本文在前人研究的基礎上提出了一系列改進方法。首先也是最重要的,我們提出了一種增強型測試程式樣板及與其對應的將測試型樣轉換為測試程式的轉換方法。該樣板可以有效提高型樣到程式轉換過程的轉換精度,從而提高測試程式的故障覆蓋率(fault coverage)。此外,我們改進了自動測試型樣產生系統的約束方法,讓只能適用於具有固定(fix-length)長度指令集架構(instruction set architecture)的處理器的測試程式生成方法也可以擴展到具有可變長度(variable-length)指令集架構的處理器。最後,我們在生成測試程式的流程中加入了程式段篩選(segment filtering)機制,有效減少了生成的測試程式大小。 所提出的技術在RV32IC處理器上得到驗證,在493KB的程式大小下實現了 91.23%的轉態延遲故障(transition delay fault, TDF)覆蓋率。與之前的研究[2]相比,此技術實現了6.65%的故障覆蓋率提高和78%的程式大小減少。 | zh_TW |
dc.description.abstract | Software-based self-test (SBST) has attracted more attention due to system reliability concerns derived from the rapid development of automotive electronics and medical electronic products. In a previous research [1], a conversion methodology based on module-independent template and constrained automatic test pattern generation (ATPG) to convert full-scan test patterns into test programs was proposed. This paper proposes a series of improved methods based on the previous work. First and foremost, we propose an enhanced template and its corresponding pattern-to-program conversion method. This template can effectively improve the conversion accuracy of the pattern-to-program conversion process, thereby improving the fault coverage (FC) of the test program. Besides, we improved the ATPG constraint method so that the test program generation method that can only be applied to processors with fix-length instruction set architecture (ISA) can also be extended to processors with variable-length instruction set architecture. Last but not least, we added a segment filtering mechanism to the program generation flow to effectively reduce the size of the generated test program. The proposed technique is validated on a RV32IC processor and achieves 91.23% transition delay fault (TDF) coverage with a program size of 493KB. Compared with the previous research [2], this technique achieved 6.65% fault coverage improvement and 78% program size reduction. | en |
dc.description.provenance | Made available in DSpace on 2023-03-19T22:18:01Z (GMT). No. of bitstreams: 1 U0001-1409202216170000.pdf: 5502458 bytes, checksum: 9424644732e35eb981c13c45a849e49a (MD5) Previous issue date: 2022 | en |
dc.description.tableofcontents | 致謝 i 摘要 ii Abstract iii 第一章序論 1 1.1 傳統製造測試的侷限性 1 1.2 內建自我測試(built-in self-test, BIST) 2 1.3 軟體自我測試(software-based self-test, SBST) 4 1.4 先前研究與研究動機 5 1.5 研究貢獻 7 1.6 論文架構 7 第二章先前研究與背景知識 8 2.1 發射捕獲圖樣(launch-on-capture pattern, LoC pattern) 8 2.2 應用於MIPS 的軟體自我測試 9 2.2.1 核心想法 9 2.2.2 自我測試程式產生器(self-test program generator) 10 2.2.3 指令集架構約束生成(ISA constraint generation) 11 2.2.4 模組無關的測試程式樣板(module-independent template) 12 2.3 不定長度的指令集架構(variable-length ISA) 13 第三章提出的方法 15 3.1 自我測試程式產生器的優化策略 15 3.2 測試圖樣到程式的轉換(pattern-to-program conversion) 16 3.2.1 改進後的樣板(modified template) 16 3.2.2 樣板開發所遇到的難題 17 3.2.3 反推管線中指令的策略 18 3.2.4 找關鍵訊息的方法 19 3.2.5 紀錄關鍵訊息 20 3.2.6 利用訊息反推管線中的指令 21 3.2.7 測試圖樣映射到指令的方法 22 3.2.8 缺失值補全 23 3.2.9 測試圖樣到程式的轉換範例 23 3.2.10 預載入序列優化 26 3.3 指令集架構約束生成(ISA constraint generation) 27 3.3.1 指令讀取機制 27 3.3.2 理想的約束方式 29 3.3.3 提出的約束方式 30 3.3.4 約束的效果 31 3.3.5 約束範例 32 3.4 程式段篩選(segment filtering) 33 3.4.1 程式段篩選的做法 34 第四章實驗結果 35 4.1 實驗設置 35 4.2 故障覆蓋率分析 36 4.3 轉換有效性分析 38 4.4 測試程式大小分析 39 4.5 運行時間分析 40 第五章結論與未來方向 42 5.1 結論 42 5.2 未來方向 42 參考文獻 43 | |
dc.language.iso | zh-TW | |
dc.title | 全管線覆蓋的自我測試程式樣板開發 | zh_TW |
dc.title | Development of Self-Test Program Template with Full Pipeline Coverage | en |
dc.type | Thesis | |
dc.date.schoolyear | 110-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李進福(Jin-Fu Li),呂學坤(Shyue-Kung Lu) | |
dc.subject.keyword | 軟體自我測試,轉態延遲故障,功能約束,測試樣板,RV32IC, | zh_TW |
dc.subject.keyword | Software-Based Self-Test,Transition Delay Fault,Functional Constraint,Test Template,RV32IC, | en |
dc.relation.page | 44 | |
dc.identifier.doi | 10.6342/NTU202203404 | |
dc.rights.note | 同意授權(限校園內公開) | |
dc.date.accepted | 2022-09-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
dc.date.embargo-lift | 2022-09-19 | - |
顯示於系所單位: | 電子工程學研究所 |
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