請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84102完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李致毅 | zh_TW |
| dc.contributor.advisor | Jri Lee | en |
| dc.contributor.author | 吳昇翰 | zh_TW |
| dc.contributor.author | Sheng-Han Wu | en |
| dc.date.accessioned | 2023-03-19T22:04:48Z | - |
| dc.date.available | 2023-11-10 | - |
| dc.date.copyright | 2022-07-26 | - |
| dc.date.issued | 2022 | - |
| dc.date.submitted | 2002-01-01 | - |
| dc.identifier.citation | [1] https://www.usb.org/
[2] https://sata-io.org/ [3] https://standards.ieee.org/ [4] Jri Lee and K. Wu, "A 20Gb/s Full-Rate Linear CDR Circuit with Automatic Frequency Acquisition," Digest of International Solid-State Circuits Conference, pp. 366-367, Feb. 2009. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84102 | - |
| dc.description.abstract | 本論文以55奈米互補式金屬氧化半導體製程實現具有符合USB3速率10Gb/s、5Gb/s 並支援 Display port 速率 8.1Gb/s、5.4Gb/s、2.7Gb/s、1.62Gb/s 之資料時脈回復電路。電路包含連續時間線性均衡器、可調增益放大器、相位偵測器、頻率偵測器、鎖定偵測器、自適應延遲校正電路、電壓控制震盪器、頻率選擇電路、帶隙參考電壓電路、1 對32 解碼器組成一資料時脈回復電路。量測上在 10Gb/s、5.4Gb/s、5Gb/s、2.7Gb/s 速率下位元錯誤偵測器驗證皆為真，功率消耗為 516mW，8.1Gb/s 與 1.62Gb/s 因為電壓控制震盪器頻率飄移無法驗證。 | zh_TW |
| dc.description.abstract | This thesis presents a clock data recovery circuit that supports USB3 and Display port data rate 10Gb/s, 5Gb/s, 8.1Gb/s, 5.4Gb/s, 2.7Gb/s, 1.62Gb/s.
The circuit includes continuous-time linear equalization (CTLE), variable gain amplifier (VGA), phase detector, frequency detector, lock detector, delay calibration, voltage-controlled oscillator (VCO), and VCO frequency band selector, bandgap reference, and 1-to-32 demultiplexer (DEMUX). In the measurement, bit error rate test at 10Gb/s, 5.4Gb/s, 5Gb/s, 2.7Gb/s is error-free. Bit error rate test at 8.1Gb/s and 1.62Gb/s failed because the VCO frequency is not covered 8.1GHz. | en |
| dc.description.provenance | Made available in DSpace on 2023-03-19T22:04:48Z (GMT). No. of bitstreams: 1 U0001-1707202216095000.pdf: 4105214 bytes, checksum: 93910af2b4cad140d15d7cc4c95cf8fd (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | 口試委員審定書 i
中文摘要 ii ABSTRACT iii CONTENT iv List of Figures v List of Tables vii Chapter 1 Introduction 1 Chapter 2 Architecture 3 Chapter 3 Building block 4 3.1 Frequency loop 4 3.1.1 Voltage controlled oscillator 4 3.1.2 Frequency band search 7 3.2 Phase detect loop 13 Chapter 4 Measurement 18 4.1 Die photo and PCB design 18 4.2 Measurement and result 21 4.3 Jitter Tolerance Measurement 26 Chapter 5 Conclusion 33 References 34 | - |
| dc.language.iso | en | - |
| dc.subject | 5Gb/s | zh_TW |
| dc.subject | 資料時脈回復電路 | zh_TW |
| dc.subject | 延遲校正電路 | zh_TW |
| dc.subject | 10Gb/s | zh_TW |
| dc.subject | 5Gb/s | en |
| dc.subject | clock data recovery circuit | en |
| dc.subject | delay calibration | en |
| dc.subject | 10Gb/s | en |
| dc.title | 應用於USB3之資料時脈回復電路 | zh_TW |
| dc.title | A Clock and Data Recovery Circuit applied for USB3 | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 110-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 謝秉璇;彭朋瑞 | zh_TW |
| dc.contributor.oralexamcommittee | Ping-Hsuan Hsieh;Pen-Jui Peng | en |
| dc.subject.keyword | 資料時脈回復電路,延遲校正電路,10Gb/s,5Gb/s, | zh_TW |
| dc.subject.keyword | clock data recovery circuit,delay calibration,10Gb/s,5Gb/s, | en |
| dc.relation.page | 34 | - |
| dc.identifier.doi | 10.6342/NTU202201510 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2022-07-18 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2022-07-26 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
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