一個採用基於電容放大技巧次取樣延遲鎖定迴路之低參考突波次取樣鎖相迴路設計

Abstract

高頻譜純度時脈之生成在一些高性能電子系統和應用中 (無線傳輸系統和資料轉換器等等)是不可或缺的。因此，主張低相位雜訊 (Phase noise)、低參考突波 (Reference spur)的鎖相迴路成為具有挑戰性的設計。次取樣 (Sub-sampling)技巧近年來被大量採用於鎖相迴路中，因其不需依靠除頻器達成上鎖，加上次取樣器的高增益，使得頻寬內相位雜訊能有很好的表現。然而，次取樣型鎖相迴路因為其機制，讓壓控振盪器受到取樣器周期性干擾，嚴重惡化生成時脈之參考突波，連帶使得電子系統中其他性能受到影響。 本論文實現了一個採用次取樣技巧之整數型鎖相迴路，來降低頻寬內的相位雜訊，此外，亦採用額外的延遲鎖相迴路，去降低取樣器對於壓控振盪器之干擾，達到良好的參考突波表現。此鎖相迴路採用 TSMC 180-nm CMOS製程實現，核心電路面積為0.051 mm2，電路操作於1.8 V，輸出頻率範圍為2.24 - 2.51 GHz。當輸入參考頻率為50 MHz，輸出頻率為2.4 GHz時，在1-MHz頻率偏移的地方相位雜訊為 -107 dBc/Hz，在頻率偏移1-kHz至10-MHz內的積分方均根抖動 (RMS jitter)為877.5 fs，參考突波為-70 dBc，核心電路功耗為4.89 mW。

Generation of high spectral purity clock is highly demanded in high-performance systems and applications, e.g., wireless communication systems and data converters. As a result, the design of low phase noise/low jitter and low reference spur phase-locked loop (PLL) has always been of great interest. Without the need for a divider and by virtue of the sub-sampling phase detector’s (SSPD) high gain, sub-sampling PLLs can achieve lower in-band phase noise and thus stand out in recent research. However, owing to the inherent operation mechanism of the SSPD, the VCO gets periodically disturbed, and hence, the output reference spur deteriorates. This would further engender harmful effects on other performance. The thesis presents an integer-N sub-sampling PLL, which achieves low in-band phase noise and low jitter. Furthermore, an auxiliary delay-locked loop (DLL) is integrated to suppress the periodic disturbance on the VCO, reaching a remarkable reference spur performance. This PLL is fabricated in TSMC 180-nm CMOS technology. The active area is 0.051 mm2. With a 50-MHz reference signal, the chip consumes 4.89 mW at 2.4 GHz from a 1.8-V power supply. The output frequency ranges from 2.24 to 2.51 GHz. Based on the measurement results, the proposed SSPLL realizes an in-band phase noise of -107 dBc/Hz at 1-MHz offset with a reference spur of -70 dBc. The integrated RMS jitter from 1-kHz to 10-MHz interval is 877.5 fs.