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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 蕭浩明 | zh_TW |
| dc.contributor.advisor | Hao-Ming Hsiao | en |
| dc.contributor.author | 吳冠廷 | zh_TW |
| dc.contributor.author | Kuan-Ting Wu | en |
| dc.date.accessioned | 2023-03-19T21:23:01Z | - |
| dc.date.available | 2023-12-26 | - |
| dc.date.copyright | 2022-07-27 | - |
| dc.date.issued | 2022 | - |
| dc.date.submitted | 2002-01-01 | - |
| dc.identifier.citation | [1] T. C. Carusone, "Introduction to digital I/O: Constraining I/O power consumption in high-performance systems", IEEE Solid-State Circuits Mag., vol. 7, no. 4, pp. 14-22, Apr. 2015. [2] Sharma, D. D. (2022, January 11). The Evolution of the PCI Express Specification: On Its Sixth Generation, Third Decade and Still Going Strong. PCISIG. https://pcisig.com/blog/evolution-pci-express-specification-its-sixth-generation-third-decade-and-still-going-strong [3] Lathi, B. P., & Ding, Z. (2010). Modern Digital and Analog Communication Systems (4th ed.). Oxford University Press. [4] J. F. Bulzacchelli, "Equalization for electrical links: Current design techniques and future directions", IEEE Solid-State Circuits Mag., vol. 7, no. 4, pp. 23-31, 2015. [5] Stephen H. Hall; Howard L. Heck, "Equalization," in Advanced Signal Integrity for High-Speed Digital Designs , IEEE, 2009, pp.499-548, doi:10.1002/9780470423899.ch12. [6] D. Menin, A. De Prà, A. Bandiziol, W. Grollitsch, R. Nonis and P. Palestri, "A Simple Simulation Approach for the Estimation of Convergence and Performance of Fully Adaptive Equalization in High-Speed Serial Interfaces," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 10, pp. 2079-2086, Oct. 2019, doi: 10.1109/TCPMT.2019.2911177. [7] S. Haykin, Adaptive Filter Theory, London, U.K.:Pearson, 2008. [8] B. Widrow and S. D. Stearns, Adaptive Signal Processing, London, U.K.:Pearson, 2003. [9] S. U. H. Qureshi, "Adaptive equalization", Proc. IEEE, vol. 73, no. 9, pp. 1349-1387, Sep. 1985. [10] J. G. Proakis and M. Salehi, Digital Communications, New York, NY, USA:McGraw-Hill, 2008. [11] J. Proakis, Digital Communications, New York:McGraw-Hill, 1995. [12] H. Higashi et al., "A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization", IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 978-985, Apr. 2005. [13] V. Stojanović et al., "Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery", IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, Apr. 2005. [14] H.-J. Chi et al., "A single-loop SS-LMS algorithm with single-ended integrating DFE receiver for multi-drop DRAM interface", IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 2053-2063, Sep. 2011. [15] J. Savoj et al., "Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20 nm CMOS", Proc. IEEE Custom Integr. Circuits Conf., pp. 1-4, Sep. 2014. [16] B. Widrow, J. M. McCool, M. G. Larimore and C. R. Johnson, "Stationary and nonstationary learning characteristics of the LMS adaptive filter", Proc. IEEE, vol. 64, no. 8, pp. 1151-1162, Aug. 1976. [17] S. U. H. Qureshi, "Adaptive equalization", Proc. IEEE, vol. 73, no. 9, pp. 1349-1387, Sep. 1985. [18] J. W. M. Bergmans, Digital Baseband Transmission and Recording, New York, NY, USA:Springer, pp. 373-450, 1996. [19] S. Chen, G. J. Gibson, C. F. N. Cowan and P. M. Grant, "Adaptive equalization of finite non-linear channels using multilayer perceptrons", Signal Process., vol. 20, pp. 107-119, Jun. 1990. [20] G. J. Gibson, S. Siu and C. F. N. Cowan, "Multilayer perceptron structures applied to adaptive equalisers for data communications", Proc. IEEE Int. Conf. Acoust. Speech Signal Process. (ICASSP), vol. 2, pp. 1183-1186, May 1989. [21] G. J. Gibson, S. Siu and C. F. N. Cowan, "The application of nonlinear structures to the reconstruction of binary signals", IEEE Trans. Signal Process., vol. 39, no. 8, pp. 1877-1884, Aug. 1991. [22] S. Chen, G. J. Gibson, C. F. N. Cowan and P. M. Grant, "Reconstruction of binary signals using an adaptive radial-basis-function equalizer", EURASIP Signal Process., vol. 22, pp. 77-93, Jan. 1991. [23] S. Panda, P. K. Mohapatra and S. P. Panigrahi, "A new training scheme for neural networks and application in non-linear channel equalization", Appl. Soft Comput., vol. 27, pp. 47-52, Feb. 2015. [24] S. Panda, A. Sarangi and S. P. Panigrahi, "A new training strategy for neural network using shuffled frog-leaping algorithm and application to channel equalization", AEU Int. J. Electron. Commun., vol. 68, no. 11, pp. 1031-1036, Nov. 2014. [25] G. Das, P. K. Pattnaik and S. K. Padhy, "Artificial neural network trained by particle swarm optimization for non-linear channel equalization", Expert Syst. Appl., vol. 41, no. 7, pp. 3491-3496, Jun. 2014. [26] P. Mohapatra, T. Samantara, S. P. Panigrahi and S. K. Nayak, "Equalization of communication channels using GA-trained RBF networks" in Progress in Advanced Computing and Intelligent Engineering, Singapore:Springer, pp. 491-499, 2018. [27] S. Haykin, Communication Systems, New York:Wiley, 1994. [28] Ratan, R. (2014). Design of a phase locked loop based clocking circuit for high speed serial link applications. [29] Mike Jackson, Ravi Budruk, Joseph Winkles, and Don Anderson. 2012. PCI Express Technology 3.0. Mindshare Press. [30] PCI SIG, “PCI Express Base Specification Revision 3.0” Version 0.9, July 20, 2010. [31] Quoc-Hoang Duong, Quan Le, Chang-Wan Kim and Sang-Gug Lee, "A 95-dB linear low-power variable gain amplifier," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 8, pp. 1648-1657, Aug. 2006, doi: 10.1109/TCSI.2006.879058. [32] Kumarhanumolu, Pavan & Wei, Gu-Yeon & Un-kumoon,. (2011). EQUALIZERS FOR HIGH-SPEED SERIAL LINKS. International Journal of High Speed Electronics and Systems. 15. 10.1142/S0129156405003259. [33] Shannon, C. E. (1949). Communication in the Presence of Noise. Proceedings of the IRE, 37(1), 10–21. https://doi.org/10.1109/jrproc.1949.232969 [34] S. Gondi and B. Razavi, "Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers," in IEEE Journal of Solid-State Circuits, vol. 42, no. 9, pp. 1999-2011, Sept. 2007, doi: 10.1109/JSSC.2007.903076. [35] B. Razavi, "The Decision-Feedback Equalizer [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 9, no. 4, pp. 13-132, Fall 2017, doi: 10.1109/MSSC.2017.2745939. [36] Mulnix, D. L. (2019, June 10). Intel® Xeon® Processor Scalable Family Technical Overview. Intel. https://www.intel.com/content/www/us/en/developer/articles/technical/xeon-processor-scalable-family-technical-overview.html [37] Intel Design-In Tool Store. (n.d.). ITP-XDP 3BR Kit. https://designintools.intel.com/product_p/itpxdp3brext.htm [38] "IEEE Standard for Test Access Port and Boundary-Scan Architecture," in IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001) , vol., no., pp.1-444, 13 May 2013, doi: 10.1109/IEEESTD.2013.6515989. [39] Technical Guide to JTAG. (n.d.). Xjtag. https://www.xjtag.com/about-jtag/jtag-a-technical-overview/ [40] 數位計時：時脈訊號、抖動、眼圖 (Eye Diagram) 概念詳解. (2019, April 16). NATIONAL INSTRUMENTS. https://www.ni.com/zh-tw/innovations/white-papers/06/digital-timing--clock-signals--jitter--hystereisis--and-eye-diag.html [41] Dally, W. J., & Poulton, J. W. (1998). Digital systems engineering. Cambridge, U.K: Cambridge University Press. [42] J. Hsu et al., "Robotic System with Intel® Automatic In-Board Characterization for Customer Board Design Quality Check," 2021 16th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2021, pp. 119-122, doi: 10.1109/IMPACT53160.2021.9696481. [43] Ali, M. (2020). PyCaret: An open source, low-code machine learning library in Python. Ανακτήθηκε από https://www.pycaret.org [44] Ke, G., Meng, Q., Finley, T., Wang, T., Chen, W., Ma, W., … Liu, T.-Y. (2017). Lightgbm: A highly efficient gradient boosting decision tree. Advances in Neural Information Processing Systems, 30, 3146–3154. [45] Ho, T. K. (1995). Random decision forests. In Proceedings of 3rd international conference on document analysis and recognition (Vol. 1, pp. 278–282). [46] Chen, T., & Guestrin, C. (2016). XGBoost: A Scalable Tree Boosting System. In Proceedings of the 22nd ACM SIGKDD International Conference on Knowledge Discovery and Data Mining (pp. 785–794). New York, NY, USA: ACM. https://doi.org/10.1145/2939672.2939785 [47] Geurts, P., Ernst, D. & Wehenkel, L. Extremely randomized trees. Mach Learn 63, 3–42 (2006). https://doi.org/10.1007/s10994-006-6226-1 [48] Freund, Y., & Schapire, R. E. (1997). A decision-theoretic generalization of on-line learning and an application to boosting. Journal of computer and system sciences, 55(1), 119-139. [49] Loh, W. Y. (2011). Classification and regression trees. Wiley interdisciplinary reviews: data mining and knowledge discovery, 1(1), 14-23. [50] Tibshirani, R. (1996). Regression shrinkage and selection via the lasso. Journal of the Royal Statistical Society: Series B (Methodological), 58(1), 267-288. [51] Hoerl, A. E., & Kennard, R. W. (1970). Ridge regression: Biased estimation for nonorthogonal problems. Technometrics, 12(1), 55-67. [52] Huber, P. J. (1992). Robust estimation of a location parameter. In Breakthroughs in statistics (pp. 492-518). Springer, New York, NY. [53] Zou, H., & Hastie, T. (2005). Regularization and variable selection via the elastic net. Journal of the royal statistical society: series B (statistical methodology), 67(2), 301-320. [54] Breiman, L. (2001). Random forests. Machine learning, 45(1), 5-32. [55] Cutler, D. R., Edwards Jr, T. C., Beard, K. H., Cutler, A., Hess, K. T., Gibson, J., & Lawler, J. J. (2007). Random forests for classification in ecology. Ecology, 88(11), 2783-2792. [56] Breiman, L. (1996). Bagging predictors. Machine learning, 24(2), 123-140. [57] Friedman, J. H. (2001). Greedy function approximation: a gradient boosting machine. Annals of statistics, 1189-1232. [58] Ruder, S. (2016). An overview of gradient descent optimization algorithms. ArXiv Preprint ArXiv:1609.04747. [59] Balasundaram, Subramanian & Prasad, subhash. (2020). Robust twin support vector regression based on Huber loss function. Neural Computing and Applications. 10.1007/s00521-019-04625-8. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83907 | - |
| dc.description.abstract | 隨著微處理器的效能提升，高速訊號的資料傳輸速度要求也越來越高，然而高速訊號速度的提升往往也會增大符碼間干擾的問題，造成訊號傳遞錯誤的情況產生。目前最主要的解決辦法便是在訊號傳送通道的兩端設置訊號補償器，為訊號提供補償以降低訊號失真的情況，針對每個通道的特性，訊號補償器的參數設定會大不相同，參數的好壞也就因此大幅的影響通訊系統的好壞，故需要設計相關的演算法搜索最佳的參數值，以確保穩定的通訊系統做後續功能性的測試，然而近年來訊號線的數量增加以及越趨複雜的補償器設計都增加了最佳參數的搜索時間。 近年來機器學習的相關技術發展相當快速，透過大數據的幫助，在各個領域都能夠協助研發人員解決以前所面臨的各式難題，故本研究提出一透過機器學習模型結合電路板電氣特性達到快速預測訊號表現的方法。 本研究所提出的預測模型共可以分為兩個部分，系統資訊之蒐集以及迴歸預測，在系統資訊蒐集的階段，會透過向量網路分析儀以及時域反射量測法兩種量測手法測量電路板各訊號線的阻抗、頻域響應等資料並做特徵擷取，另外也設計了訊號餘裕實驗測量每條訊號線在不同的訊號補償器設置下的訊號表現，將上述的兩種資料整合後，在迴歸預測的部分，會做為訓練資料用以訓練各種機器學習模型，使得模型能夠根據訊號線的電氣特性預測出不同訊號補償器參數下的訊號餘裕值。經過本研究的相關實驗與分析，成功地訓練出一能在短時間內預測訊號餘裕的模型，透過此方法便能夠快速地降低訊號補償器最佳參數地搜索時間，降低電路板開發、驗證的時間。 | zh_TW |
| dc.description.abstract | With the improvement of the performance of microprocessors, the data transmission speed of high-speed signal is also getting higher and higher. However, the improvement of high-speed signal speed often aggravate the problem of inter-symbol interference, resulting in the occurrence of signal transmission errors. The main solution is to set up signal equalizers at both ends of the signal transmission channel to provide compensation for the signal to reduce signal distortion. According to the characteristics of each channel, the parameter settings of the signal equalizers are very different. The parameter settings therefore greatly affect the quality of the communication system. Thus, it is necessary to design algorithms to search for the best parameter to ensure a stable communication system for subsequent functional validation tests. However, recently, the number of signal lines has increased and more complex signal equalizer designs lead to greater search time for optimal parameters. In recent years, the technologies of machine learning have developed rapidly. With the help of big data, several difficult problems in various fields could be solved. Therefore, this study proposes a machine learning model combined with the electrical characteristics of the circuit board to predict signal performance. The prediction model proposed in this study can be divided into two parts, the collection of system information and the regression prediction. First, the impedance, and frequency response of each signal line on the circuit board are measured by Vector Network Analyzer (VNA) and Time Domain Reflectometry (TDR). The feature vectors are then extracted for following training. In addition, a signal margin validation test is designed to measure the signal margin of each signal line under different signal equalizer settings. After integrating the data, they are used to train various machine learning models. The models can predict the signal margin under different signal equalizer parameters according to the electrical characteristics of the signal line. After the relevant experiments and analysis, a model that can predict the signal margin in a short time has been successfully trained. This proposed methodology can reduce the search time for the optimal parameters of the signal compensator, and thus reduce the development and validation time of printed circuit board. | en |
| dc.description.provenance | Made available in DSpace on 2023-03-19T21:23:01Z (GMT). No. of bitstreams: 1 U0001-1107202217374000.pdf: 3782114 bytes, checksum: a40e732fb4fb09a2e94e2a1764e1fbb7 (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | 口試委員審定書 i 摘要 ii Abstract iii 目錄 v 圖目錄 vii 表目錄 x 第一章、 緒論 1 1.1 前言 1 1.2 研究目的 2 1.3 研究內容與本文架構 2 第二章、 文獻探討 5 2.1 訊號補償 5 2.2 傳送端訊號補償 6 2.3 接收端訊號補償 9 2.3.1 自動增益控制 10 2.3.2 連續時間性線性均衡器 12 2.3.3 決策回饋等化器 16 第三章、 電子訊號之量測實驗及資料收集 19 3.1 訊號餘裕實驗環境之硬體簡介 19 3.1.1 Ultra Path Interconnect 20 3.1.2 eXtended Debug Port 21 3.1.3 Joint Test Action Group 22 3.2 訊號餘裕實驗環境之軟體簡介 24 3.2.1 眼圖 25 3.2.1 系統初始化設置 26 3.2.2 時間餘裕測試 28 3.2.3 電壓餘裕測試 32 3.2.4 接收端訊號補償參數 35 3.3 Automatic In-Board Characterization 37 3.3.1 時域反射量測法 37 3.3.2 向量網路分析儀 39 3.3.3 AIBC量測訊號後處理 42 第四章、 訊號餘裕表現預測 43 4.1 迴歸模型 43 4.1.1 決策樹型迴歸模型 44 4.1.2 線性迴歸模型 52 4.2 迴歸結果 56 第五章、 結論與未來展望 67 5.1 結論 67 5.2 未來展望 68 參考資料 69 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 訊號量測 | zh_TW |
| dc.subject | 機器學習 | zh_TW |
| dc.subject | 電路板驗證 | zh_TW |
| dc.subject | 訊號量測 | zh_TW |
| dc.subject | 訊號補償 | zh_TW |
| dc.subject | 機器學習 | zh_TW |
| dc.subject | 電路板驗證 | zh_TW |
| dc.subject | 訊號補償 | zh_TW |
| dc.subject | signal measurement | en |
| dc.subject | machine learning | en |
| dc.subject | signal equalization | en |
| dc.subject | machine learning | en |
| dc.subject | validation of printed circuit board | en |
| dc.subject | signal measurement | en |
| dc.subject | signal equalization | en |
| dc.subject | validation of printed circuit board | en |
| dc.title | 應用機器學習於高速訊號穩定度之智慧檢測系統 | zh_TW |
| dc.title | Smart Detection System for High-Speed Signal Stability Using Machine Learning | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 110-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 楊士進;陳湘鳳 | zh_TW |
| dc.contributor.oralexamcommittee | Shih-Chin Yang;Shana Smith | en |
| dc.subject.keyword | 訊號補償,訊號量測,電路板驗證,機器學習, | zh_TW |
| dc.subject.keyword | signal equalization,signal measurement,validation of printed circuit board,machine learning, | en |
| dc.relation.page | 75 | - |
| dc.identifier.doi | 10.6342/NTU202201407 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2022-07-12 | - |
| dc.contributor.author-college | 工學院 | - |
| dc.contributor.author-dept | 機械工程學系 | - |
| 顯示於系所單位： | 機械工程學系 | |
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