0.6伏十二位元50-kS/s之逐漸趨近式類比數位轉換器設計及應用於腦深層刺激系統之腦電訊號量測與刺激模組設計

Abstract

癲癇為一種起因於大腦皮質神經細胞活動過度或放電異常而產生的神經系統疾病，為減輕此疾病對患者之影響，許多文獻提出不同種類的腦電訊號感測與回授系統，監測患者之腦電訊號並在癲癇發生時甚至發生前給予電或光刺激。根據之前的這些研究，本論文針對腦電訊號感測與回授系統及應用於腦電訊號感測之類比數位轉換器進一步進行研究與設計。 本論文可分為兩個部分，第一部分完成一個利用市售元件組成之無線腦電訊號監測與刺激系統，此系統包含使用者介面、癲癇偵測演算法、藍芽無線傳輸電路、腦電訊號感測電路、光刺激與電刺激電路及電源管理電路。為了驗證此系統功能，亦對此系統的各個部份進行量測。除此之外，也執行動物實驗證明此系統在臨床實驗之可行性。 第二部分則為用於癲癇監測系統之類比數位轉換器的晶片設計與量測。前段實作一顆採用台積電180奈米製程的3.3伏特供應電源12位元逐漸趨近式類比數位轉換器，以及利用此類比數位轉換器與八通道前端訊號放大電路和彭盛裕教授實驗室提供之四通道電刺激電路整合的台積電180奈米製程系統晶片。除此之外，本論文研究亦改良前述之逐漸趨近式類比數位轉換器，結合節省功率消耗之跳躍式視窗架構與解決電容不匹配之離散傅立葉轉換校正，並為了進一步降低功率消耗而將供應電壓降至0.6伏，實現一個和前一次的類比數位轉換器相比，功耗更低及性能上更優化的12位元逐漸趨近式類比數位轉換器。

Epilepsy is a kind of nervous system disease due to excessive or abnormal electrical activities of the neurons in cerebral cortex. To alleviate the impact of this disease to the patients, different kinds of electroencephalography (EEG) sensing and feedback systems have been proposed by several studies to monitor the EEG signal and perform the electrical or optogenetic stimulation during or even before the epileptic seizure. Based on these previous works, this thesis focuses on the study and design of the EEG sensing and feedback system and the analog-to-digital converter (ADC) for the EEG signal recording. This thesis can be divided into two parts. The first part is the realization of a wireless EEG signal recording and stimulation system utilizing off-the-shelf components. This system includes the user interface, Bluetooth wireless transmission circuit, EEG signal sensing circuit, optogenetic stimulation circuit, electrical stimulation circuit, and power management circuit. To verify the function of this system, several measurements on different parts of this system have been conducted. In addition, animal experiments have been performed to prove the feasibility of the proposed system on clinical trials. The second part is the chip design and measurements of the ADCs for the epilepsy monitoring system. The forepart is the implementation of a 12-bit successive-approximation register (SAR) ADC with 3.3-V supply voltage fabricated in TSMC 180-nm process. This SAR ADC was also integrated with 8-channel analog front-end amplification circuit and 4-channel stimulator from professor Sheng-Yu Peng’s lab. The integrated chip was also fabricated in TSMC 180-nm process. Besides, this thesis also improves the previous SAR ADC by combining the bypass window technique for power reduction and discrete-time-Fourier-transform-based calibration for the capacitor mismatch issue. The supply voltage of this ADC is also scaled down to 0.6 V to further reduce the power consumption. The new 12-bit SAR ADC exhibits lower power consumption and better performance compared to the previous one.