請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83629完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模 | zh_TW |
| dc.contributor.advisor | Chien-Mo Li | en |
| dc.contributor.author | 郭承賢 | zh_TW |
| dc.contributor.author | Cheng-Sian Kuo | en |
| dc.date.accessioned | 2023-03-19T21:12:24Z | - |
| dc.date.available | 2023-12-25 | - |
| dc.date.copyright | 2022-08-31 | - |
| dc.date.issued | 2022 | - |
| dc.date.submitted | 2002-01-01 | - |
| dc.identifier.citation | [1] S. Kundu, “Diagnosing scan chain faults,” IEEE Transactions on Very Large Scale Integration Systems, vol. 2, no. 4, pp. 512–516, 1994. [2] J.-S. Yang and S.-Y. Huang, “Quick scan chain diagnosis using signal profiling,” in International Conference on Computer Design, pp. 157–160, IEEE, 2005. [3] Y. Huang, R. Guo, W.-T. Cheng, and J. C.-M. Li, “Survey of Scan Chain Diagnosis,” IEEE Design & Test of Computers, vol. 25, no. 3, pp. 240–248, 2008. [4] V. Chickermane, B. Foutz, and B. Keller, “Channel masking synthesis for efficient on-chip test compression,” in 2004 International Conferce on Test, pp. 452–461, 2004. [5] P. Wohl, J. Waicukauski, and S. Ramnath, “Fully x-tolerant combinational scan compression,” in 2007 IEEE International Test Conference, pp. 1–10, 2007. [6] X. Tang, R. Guo, W.-T. Cheng, and S. M. Reddy, “Improving compressed test pattern generation for multiple scan chain failure diagnosis,” in Design, Automation & Test in Europe Conference Exhibition, pp. 1000–1005, 2009. [7] S. Kundu, S. Chattopadhyay, I. Sengupta, and R. Kapur, “Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment,” IEEE Transactions on Very Large Scale Integration Systems, vol. 23, no. 7, pp. 1185–1195, 2015. [8] S. Kundu, K. Kumar, R. Kumar, and R. Kapur, “Diagnosing multiple faulty chains with low pin convolution compressor using compressed production test set,” in International Test Conference, pp. 1–7, 2017. [9] A. Chandra, R. Kapur, and Y. Kanzawa, “Scalable Adaptive Scan (SAS),” in Design, Automation & Test in Europe Conference Exhibition, pp. 1476–1481, 2009. [10] Y.-l. Kao, W.-s. Chuang, and J. C.-m. Li, “Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis,” in International Test Conference, pp. 1–9, 2006. [11] K. Stanley, “High-accuracy flush-and-scan software diagnostic,” IEEE Design & Test of Computers, vol. 18, no. 6, pp. 56–62, 2001. [12] R. Guo and S. Venkataraman, “A technique for fault diagnosis of defects in scan chains,” in International Test Conference, pp. 268–277, IEEE, 2001. [13] J. C.-M. Li, “Diagnosis of single stuck-at faults and multiple timing faults in scan chains,” IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 6, pp. 708–718, 2005. [14] J.-M. Li, “Diagnosis of multiple hold-time and setup-time faults in scan chains,” IEEE Transactions on Computers, vol. 54, no. 11, pp. 1467–1472, 2005. [15] K. De and A. Gunda, “Failure analysis for full-scan circuits,” in International Test Conference, pp. 636–645, IEEE, 1995. [16] P. Song, F. Stellari, T. Xia, and A. J. Weger, “A novel scan chain diagnostics technique based on light emission from leakage current,” in International Test Conference, pp. 140–147, IEEE, 2004. [17] S. Edirisooriya and G. Edirisooriya, “Diagnosis of scan path failures,” in IEEE VLSI Test Symposium, pp. 250–255, IEEE, 1995. [18] Y. Wu, “Diagnosis of scan chain failures,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 217–222, IEEE, 1998. [19] R. Tekumulla and D. Lee, “On identifying and bypassing faulty scan segments,” in Proc. North Atlantic Test Workshop, pp. 134–143, 2007. [20] Y. Huang, W.-T. Cheng, and R. Guo, “Diagnose multiple stuck-at scan chain faults,” in European Test Symposium, pp. 105–110, IEEE, 2008. [21] Y. Huang, H.-Y. Tseng, W.-T. Cheng, A. Huang, C.-J. Hsieh, and Y.-T. Hung, “Efficient diagnosis for multiple intermittent scan chain hold-time faults,” in Asian Test Symposium, pp. 44–49, IEEE, 2003. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83629 | - |
| dc.description.abstract | 掃描鏈診斷在提升產品良率的過程中扮演關鍵的腳色。現今電路設計中使用的高掃描鏈壓縮比增加了掃描鏈診斷的挑戰。擁有多重故障掃描鏈出現在同一個壓縮器底下已經成為現實。在同一個壓縮器底下，我們觀察到擁有兩條故障掃描鏈的機率大於擁有兩條以上的故障掃描鏈機率。在我們檢查的44個設計中，前一種情況的平均故障晶片百分比為8.76%, 而後一種情況的平均百分比為13.99%。這帶來了研究為同一台壓縮機提供雙重故障掃描鏈解決方案的急迫性。我們提出了一種技術來幫助解決這個問題，分離鏈故障效應的疊加以診斷具有雙重故障掃描鏈的晶片。此技術首先使用跳躍模擬來識別和分類僅歸因於一個故障鏈的故障。接著我們使用商業工具分別診斷已被分類到每個鏈的故障。為了證明我們技術的有效性，我們在模擬和真實測試數據上進行了實驗，所提出的方法顯示在解析度（2.38個候選者）和準確度（92.0%）方面相較使用商業工具的標準診斷有所改進。我們確實在生產測試中發現了10個故障晶片，它們可能在相同的雙重掃描鏈中存在系統性問題。 | zh_TW |
| dc.description.abstract | Diagnosing scan chain faults plays a key role in ramping up production yield. High scan chain compression ratios of modern designs increase the challenge of scan chain diagnosis. Having multiple faulty chains feeding the same compressor becomes a reality. Under the same compressor, we observe that the probability of having two faulty chains is higher than that of having more than two faulty chains. Among 44 designs we examined, the average percentage of failing devices for the former is 8.76%, while for the latter is 13.99%. This brings the urgency of investigating a solution for double faulty chains feeding the same compressor. We propose a technique to help address this problem, separating the superposition of chain fault effects to diagnose chips with two faulty scan chains. This technique first uses jump simulation to identify and classify failures that are attributable to only one of the faulty chains. Then we use commercial tools to diagnose the classified failures of each chain individually. To demonstrate the efficacy of our technique, experiments are conducted on both simulated and silicon test data, and the proposed method showed improvements over standard diagnosis with commercial tools in resolution (2.38 candidates) and accuracy (92.0%). We did find ten failing chips that potentially have a systematic problem in the same double chains in the production test. | en |
| dc.description.provenance | Made available in DSpace on 2023-03-19T21:12:24Z (GMT). No. of bitstreams: 1 U0001-1908202211024200.pdf: 1411367 bytes, checksum: 24b77f80394c278d8e46952f2f6367f4 (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | 目錄： 口試委員審定書 (i) 致謝 (ii) 摘要 (iv) Abstract (v) Contents (vi) List of Figures (viii) List of Tables (x) Chapter 1 Introduction (1) 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Proposed Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 2 Background (10) 2.1 Scan Chain Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Test Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Jump Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 3 Proposed Techniques (20) 3.1 DOC Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 F1 suspected Jump Bits Identification . . . . . . . . . . . . . . . . . . 24 3.3 Diagnosis of One Chain Fault at a Time . . . . . . . . . . . . . . . . 30 3.4 Candidate Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Chapter 4 Experimental Results (35) 4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2 Experiments on Simulated Data . . . . . . . . . . . . . . . . . . . . 36 4.3 Experiments on Silicon Data . . . . . . . . . . . . . . . . . . . . . . 40 4.4 Runtime Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Chapter 5 Discussion (45) 5.1 Triple Faulty Chains Diagnosis (TFCD) Problem . . . . . . . . . . . 45 5.2 Multiple Faulty Chains Diagnosis (MFCD) Problem . . . . . . . . . 50 Chapter 6 Conclusion (55) References (57) 圖目錄： 1.1 Superposition of fault effects . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Diagnosis of one chain fault at a time . . . . . . . . . . . . . . . . . . . 6 2.1 Test time (without vs with test compression) . . . . . . . . . . . . . . . . 13 2.2 Space compressor (XOR tree) . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Time compressor (MISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 Convolutional compressor . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 Compression aliasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 Solve compression aliasing and fault effects superposition by one-hot test 18 3.1 Overall flow for systematic DFCD problems . . . . . . . . . . . . . . . . 21 3.2 Illustration of DOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 Evaluating similarity of distinguishing FBs . . . . . . . . . . . . . . . . 27 3.4 Similarity of different jump bits . . . . . . . . . . . . . . . . . . . . . . 29 3.5 Diagnosis of one chain fault at a time (example) . . . . . . . . . . . . . . 30 5.1 Three scenarios for TFCD problem . . . . . . . . . . . . . . . . . . . . . 47 5.2 Remove potential FBs for F1 . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3 Illustration of information loss after removing FBs . . . . . . . . . . . . 51 5.4 FBs percentage of different failing patterns . . . . . . . . . . . . . . . . 52 5.5 Overall flow for systematic MFCD problems . . . . . . . . . . . . . . . 54 表目錄： 1.1 Statistic of fail logs with multiple faulty chains feeding the same compressor 2 3.1 Evaluation results of TFA and JSF of jump bit 140 . . . . . . . . . . . . 29 3.2 Example to remove FBs . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1 Design information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2 Coarse identification results of simulated data . . . . . . . . . . . . . . . 37 4.3 Fine identification results of simulated data . . . . . . . . . . . . . . . . 38 4.4 Results of simulated data by three methods . . . . . . . . . . . . . . . . 40 4.5 Coarse identification results of silicon data (Design A) . . . . . . . . . . 41 4.6 Costs and results of diagnosing silicon data (Design A) . . . . . . . . . . 43 4.7 Runtime overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.1 TFCD experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 | - |
| dc.language.iso | en | - |
| dc.subject | 系統性缺陷 | zh_TW |
| dc.subject | 掃描壓縮 | zh_TW |
| dc.subject | 系統性缺陷 | zh_TW |
| dc.subject | 掃描鏈診斷 | zh_TW |
| dc.subject | 掃描壓縮 | zh_TW |
| dc.subject | 掃描鏈診斷 | zh_TW |
| dc.subject | systematic defect | en |
| dc.subject | scan chain diagnosis | en |
| dc.subject | scan compression | en |
| dc.subject | systematic defect | en |
| dc.subject | scan chain diagnosis | en |
| dc.subject | scan compression | en |
| dc.title | 診斷雙重故障掃描鏈透過錯誤位元分離 | zh_TW |
| dc.title | Diagnosing Double Faulty Chains through Failing Bit Separation | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 110-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 黃錫瑜;饒建奇 | zh_TW |
| dc.contributor.oralexamcommittee | Shi-yu Huang;Jiann-chyi Rau | en |
| dc.subject.keyword | 掃描鏈診斷,掃描壓縮,系統性缺陷, | zh_TW |
| dc.subject.keyword | scan chain diagnosis,scan compression,systematic defect, | en |
| dc.relation.page | 59 | - |
| dc.identifier.doi | 10.6342/NTU202202574 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2022-08-22 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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