消除遠端串音干擾之發射器電路和設計自動化

Abstract

迎來高速晶片通信時代，主要挑戰之一是在存在各種干擾的情況下仍能夠保持信號完整性。本論文的重點是解決遠端串音干擾 (FEXT)，這是一個在數據速率不斷攀升的過程中令人煩惱的問題，尤其是在通信通道越來越近的情況下。它不僅改變了信號在接收端 (RX) 的到達時間，而且擾亂了接收信號的電壓值。此外，由於遠端串音引起的抖動 (CIJ)，錯碼率 (BER) 會變得更高。針對這個問題，本文提出了一個完整的解決方案。從將通道的 s 參數排序為 4×4 矩陣開始，然後由反矩陣中找到抵消串音的項目。串音消除項 (XTC) 將由一階近似技術進行仿真，而後轉換在發送器端 (TX) 上藉由調整訊號的迴轉率實現電路。本文所提出的發射器是使用 28 nm CMOS 工藝實現的。模擬顯示，在 8 Gb/s 的PRBS ，數據速率為 2^7-1 和0.01 英寸的傳輸線間距下，能夠完整消除遠端串音所貢獻的時脈等動。測量結果表明，在 4 Gb/s PRBS ，數據速率為 2^7-1 和0.01 英寸的傳輸線間距下，能夠消除大約一半的遠端串音所貢獻的時脈等動。此外，所提出的方案亦可以應用在多於兩條的傳輸線上。 此外，在我看來，發射器本質上是一種數位類比轉換器 (DAC) 設計。 DAC的核心部分是一個井然有序的金氧半導體場效電晶體（MOS）陣列，可以按行數和列數排列。因此，構建MOS陣列的過程可以很容易地與基於程式的設計方法相關聯。在本論文中，柏克萊大學-類比電路產生器（BAG）將被應用在構建 MOS 陣列中。該設計套件旨在自動化設計過程，包括電路生成、寄生效應萃取和驗證。利用該套件，MOS 陣列的生成變得快速且可編碼，從大約 1 到 2 周的時間縮短到僅 30 分鐘。因此，它為我們提供了另一種不同的IC設計方法。

Ushering in the high-speed chip-to-chip communication era, one of the primary challenges is to maintain the signal integrity in the presence of various noise. This thesis focuses on far-end crosstalk (FEXT), which is an annoying issue while the data rate is continuously climbing up, especially if the communication channels are placed closer and closer. It not only shifts the arriving time of the signal in the receiver end (RX), but also perturbs the voltage level of the received signal. Thus, the bit-error rate (BER) will get higher due to the crosstalk-induced jitter (CIJ). To address this issue, this thesis proposes a solution from top to bottom. Starting from ordering the s parameter of the channel into a 4-by-4 matrix, then find the crosstalk cancelling terms in the inverse matrix imposed on those 4-by-4 matrices. The crosstalk cancellation (XTC) term will be emulated by a first-order approximation technique, which will therefore be converted to the circuit implementing on the transmitter end (TX) by controlling the slew rate of the signal. The proposed TX was implemented by using a 28 nm CMOS process. The simulation shows that the proposed TX reduces the RX jitters by about 12 ps (nearly 100% of the added jitter due to CIJ) at the data rate of 8 Gb/s PRBS of 2^7-1 and 0.01 inch channel spacing. And the measurement shows that the proposed transmitter reduces the RX jitters by about 30 ps (nearly 50% of the added jitter due to CIJ) at the data rate of 4 Gb/s PRBS of 2^7-1 and 0.01 inch channel spacing. The proposed scheme can be applied to more than two parallel microstrip lines. Moreover, in my point of view, transmitter is essentially a digital-to-analog converter (DAC) design. The core part of DAC is an orderly metal-oxide semiconductor field-effect transistor (MOS) array that could be arranged by the row number and column number. Therefore, the procedure of constructing the MOS-array can be easily associated with the code based design method. In this thesis, Berkeley Analog Generator (BAG) will be included in building the MOS-array. This design kit aims to automate the design procedure, including circuit generation, extraction and verification. By leveraging this kit, the generation of the MOS-array becomes rapid and codable, from about 1 to 2 weeks to only 30 minutes. Thereby, it offers us another IC design method in different light.