應用於32-Gb/s不歸零碼接收器與112-Gb/s四階脈衝振幅調變接收器之電路設計

Abstract

近年來由於物聯網、資料中心、人工智慧、機器學習等紛紛興起，面臨龐大的待處理資料，通訊系統對資料傳輸速率的要求呈現飛躍性的成長，包含SATA、PCIe、USB、乙太網路等，這種情況造就各種規格下的有線傳輸都必須縮短其世代更新的週期，以因應不斷推陳出新的各種應用。 作為個人電腦、伺服器及儲存裝置基礎I/O介面的PCIe，幾乎所有周邊裝置或其他I/O介面，都是透過PCIe來與運算核心連結。回顧PCIe協定的發展歷史，從PCIe1.0(2.5GT/s,2003)到PCIe3.0(8GT/s,2010)期間約是三至四年進行一次世代更新，更新至PCIe4.0(16GT/s,2017)卻花了七年的時間，我認為這是因為當時對於算力及資料傳輸速率的需求還沒有那麼緊湊。催生PCIe4.0推出的時間點恰巧是人工智慧、機器學習、邊緣運算等需要強力算力與資料傳輸速率的應用流行起來的時間點，而後僅花了兩年的時間PCIe5.0(32GT/s)便推出以支援這些新的應用。 作為各種規格的高速有線傳輸背後的核心技術SerDes，接收器在其中更是尤為重要的一塊。本論文所提出之32Gb/s不歸零碼接收器便是基於PCI-SIG所制定之PCIe5.0規格下所提出的設計，其中包含了基於反向器設計之連續時間等化器、基於反向器設計之可編程增益放大器、八個抽頭其中包含四個固定與四個可調整之決斷反饋等化器、一個抽頭的前饋式等化器、基於相位內插器之數位時脈資料回復電路及鎖相迴路，使用台積電12奈米工藝技術製造。PCIe5.0推出的三年後PCIe6.0(64GT/s)也在2022年推出，面臨如此高速的資料傳輸速率傳統的不歸零碼資料型式通道損耗過大，因此在PCIe6.0的世代將會全面啟用四階脈衝振幅調變的資料型式。本論文亦提出了一個以台積電40奈米工藝技術製造之80Gb/s四階脈衝振幅調變接收器，其中包含連續時間等化器、一個抽頭的前饋式等化器及一個抽頭的預測決斷反饋等化器。

In recent years, due to the rise of the Internet of Things, data centers, artificial intelligence, machine learning, etc., facing the massive amount of data to be processed, the data transmission rate requirements of communication systems have shown rapid growth, including SATA, PCIe, USB, and Ethernet networks, etc. The wireline communication under various specifications must shorten the cycle of its generational update in order to cope with the continuous introduction of new applications. PCIe is the primary I/O interface of personal computers, servers, and storage devices. Almost all peripheral devices or other I/O interfaces are connected to the computing core through PCIe. Looking back at the development history of the PCIe protocol, from PCIe 1.0 (2.5GT/s, 2003) to PCIe 3.0 (8GT/s, 2010), a generational update was performed every three to four years, and it was updated to PCIe 4.0 (16GT/s, 2017), but it took seven years. I think this is because the demand for computing power and the data transfer rate were not so tight at that time. The launch of PCIe 4.0 coincides with the time when applications that require powerful computing power, such as artificial intelligence, machine learning, and edge computing, have become popular. Then it took only two years for PCIe 5.0 (32GT/s) to be launched to support these new applications. As the core technology behind the high-speed wireline communication of various specifications, SerDes, the receiver, is a critical piece. The 32Gb/s non-return-to-zero code receiver proposed in this paper is based on the design proposed under the PCIe5.0 specification formulated by PCI-SIG, which includes a continuous-time equalizer based on an inverter design, an inverter-based programmable gain amplifier, eight taps including four fixed and four adjustable decision feedback equalizers, one tap feedforward equalizer, digital clock data recovery based on phase interpolator and PLL.The circuits are fabricated in TSMC's 12nm process technology. Three years after PCIe5.0 was launched, PCIe6.0 (64GT/s) will also be launched in 2022. In the face of such a high-speed data transmission rate, the traditional NRZ data transmission type channel loss is too significant so that the PCIe6.0 generation will be Fully enabled fourth order pulse amplitude modulation data type. This paper also proposes an 80Gb/s PAM4 receiver fabricated on TSMC's 40nm process technology, which includes a continuous-time equalizer, a one-tap feed-forward equalizer, and a one-tap look-ahead decision Feedback equalizer.