全數位校正的高解析度連續漸進式類比至數位轉換器

Abstract

為了可以以數位的方式處理信號，類比數位轉換器是自然界訊號與數位領域的重要介面。本論文提出了一個每秒一百萬次取樣的十六位元連續漸進式類比數位轉換器並使用電容誤差以及平移誤差校正。 比較器在類比數位轉換器中扮演非常重要的角色，常見的比較器架構很難達到所需的規格。環形比較器可以實現低雜訊，且可以動態調整功耗。高解析度的類比數位轉換器中的電容陣列非常大，這會使得切換電容能量效率較差。為了降低切換能量，使用了偵測與迴避切換及同步切換。此外，使用小的單位電容同樣可以有效降低切換能量，但電容誤差則是一大問題。分離式權重補償技巧可以解決該問題，而背景平移誤差校正可以處理次區間架構的平移誤差。 本文提出的類比數位轉換器在0.9伏特的供給電壓下，模擬時功耗為40.77微瓦，在加上瞬時雜訊模擬中訊號對雜訊失真比為85.49分貝，而Schreier品質因數及Walden品質因數分別為186.39dB以及每步階轉換消耗2.65飛焦耳。

To process the signal in the digital domain, an analog-to-digital converter (ADC) is a critical interface between the natural world and the digital domain. This thesis presents a 16-bit 1MS/s sub-ranging successive approximation register (SAR) ADC with capacitor and offset mismatch calibration. In order to achieve 16-bit resolution, the comparator plays a critical role. It is difficult for commonly used comparator architecture to achieve the specification. The ring comparator in the fine ADC can achieve low input referred noise and dynamic saving power. The capacitor array is large in high-resolution SAR ADC, and it will cause the switching to be not energy efficient. In order to reduce the switching energy, the detect-and-skip (DAS) and aligned switching (AS) method are used. Furthermore, using a small unit capacitor can also save the switching energy, but the capacitor mismatch will become an issue. Weight-split compensation can overcome the capacitor mismatch issue, and the background offset calibration can deal with the offset mismatch in the sub-ranging architecture. In the simulation, the proposed ADC consumes 40.77uW under 0.9V supply voltage, the SNDR is 85.49dB with the transient noise, the FoMS is 186.38dB and FoMW is 2.65fj/conversion step, respectively.