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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/82226完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
| dc.contributor.author | Po-Wei Chen | en |
| dc.contributor.author | 陳柏瑋 | zh_TW |
| dc.date.accessioned | 2022-11-25T06:33:59Z | - |
| dc.date.copyright | 2022-02-17 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2022-01-11 | |
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Faccio, and E. Palange, “An FPGA-Based Architecture of True Random Number Generator for Network Security Applications”, IEEE International Symposium on Circuits and Systems(ISCAS), 2018. [6] S. Choi, Y. Shin, and H. Yoo, “Analysis of Ring-Oscillator-based True Random Number Generator on FPGAs”, International Conference on Electronics, Information, and Communication(ICEIC), 2021. [7] Y. Ho, Y. S. Yang, C. Chang, and C. Su, “A Near-Threshold 480MHz 78μW All-Digital PLL With a Boostrapped DCO”, IEEE Journal of Solid-State Circuits, vol. 48, no.11, pp. 2805-2814, Nov. 2013. [8] B. M. Helal, C. M. Hsu, K. Johnson, and M. H. Perrott, “A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop”, IEEE Journal of Solid-State Circuits, vol. 44, no.5, pp. 1391-1400, May. 2009 [9] W. Yan, H. Zhu, Z. Yu, F. Tehranipoor, J. Chandy, and N. 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Onoye, “Jitter amplifier for oscillator-based true random number generator”, Asia and South Pacific Design Automation Conference, pp. 81-82, 2011. [14] J. Lee, H. Wang, “Study of Subharmonically Injection-Locked PLLs”, IEEE Journal of Solid-State Circuits, vol. 44, no.5, pp. 1539-1553, May. 2009. [15] S. Rethinam, S. Rajagopalan, S. Janakiraman, and S. Arumugham, “Jitters through dual clocks : An effective Entropy Source for True Random Number Generation”, International Conference on Computer Communication and Informatics(ICCCI), Jan. 2018. [16] S. Taneja, V. K. Rajanna, Massimo, Alioto, “Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security”, IEEE International Solid-State Circuits Conference (ISSCC), pp. 498-499, Feb. 2021. [17] E.N. Allini, O. Petura, V. Fischer, and F. Bernard, “Optimization of the PLL configuration in a PLL-based TRNG design”, Design, Automation Test in Europe Conference Exhibition (DATE), 2018. [18] N. Jiteurtragool, C. Wannaboon, and T. Masayoshi, “True Random Number Generator Based on Compact Chaotic Oscillator”, International Symposium on Communications and Information Technologies, pp. 315-318, 2015. [19] Y. C. Huang, and S. I. Liu, “A 2.4 GHz sub-harmonically injection-locked PLL with self-calibrated injection timing”, IEEE Journal of Solid-State Circuits, vol. 48, no.2, pp. 417-428, Feb. 2013. [20] S. Robson, B. Leung, and G. Gong, “Truly Random Number Generator Based on a Ring Oscillator Utilizing Last Passage Time”, IEEE Transactions on Circuits and Systems, vol. 61, no.12, Dec. 2014. [21] X. Wang, Huaguo Liang, Y. Wang, L.Yao, and Y. Guo, “High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure”, vol. 68, no.2, pp. 741-750, Feb. 2021. [22] J. Kil, J. Gu, and C. H. Kim, “A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting”, IEEE Transactions on Very Large Scale Integration(VLSI) Systems, vol. 16, no. 4, pp. 456-465, Apr. 2008. [23] C. F. Liang and K. J. Hsiao, “An injection-locked ring PLL with self-aligned injection window”, IEEE International Solid-State Circuits Conference (ISSCC), pp. 90-92, Feb. 2011. [24] S. I. Liu, C. Y. Yang, 鎖相迴路. Tsang Hai Book Publishing Co., 2006. [25] K. Yang, D. Blaauw, and D. Sylvester, “A Robust -40 to 120℃ All-Digital True Random Number Generator in 40nm CMOS”, Symposium on VLSI Circuits (VLSI Circuits), 2015. [26] Y. T. Lin, Y. S. Lin, C. H. Chen, H. C. Chen, Y. C. Yang, and S. S. Lu, “A 0.5-V Biomedical System-on-a-Chip for Intrabody Communication System”, IEEE Transactions on Industrial Electronics, vol. 58, no.2, pp.690-699, Feb. 2011. [27] P. Z. Wieczorek, K. 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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/82226 | - |
| dc.description.abstract | "近年來，5G通訊蓬勃發展，隨著製程及物聯網技術的不斷進步，產品也越來越注重在小面積的趨勢，各電子產品也會受限於電池的壽命長短，因此低功耗的設計越顯得更加重要。 根據International Technology Roadmap for Semiconductor (ITRS) 的研究報告，下一低功耗世代，供應電壓將下降至0.5V。鎖相迴路（Phase-Locked Loop, PLL）在許多電路中扮演著不可或缺的角色，低電壓的PLL將成為相當重要的研究。 本論文提出一個透過鎖相迴路產生的輸出波型去實現亂數產生器，晶片採用 0.5V 台積電的90nm CMOS標準製程實現，晶片面積和核心面積分別為0.558 〖mm〗^2 和0.062 〖mm〗^2，我提出一個操作在供應電壓0.5伏特，透過自動注入的鎖相迴路產生出的輸出波型，再透過兩級D flip-flop產生出的亂數波型，接著去測量商熵( entropy )大小值，以達到亂數產生器的實現，根據NIST SP800-90B，透過Ubuntu的測量最後產生出來的亂數波型後，熵( entropy) 的值為0.517。 " | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-25T06:33:59Z (GMT). No. of bitstreams: 1 U0001-0601202222442500.pdf: 2529088 bytes, checksum: e69bff6d702d372bd11828d58707277f (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | 口試委員審定書 i 誌謝 ii 中文摘要 iii ABSTRACT iv CONTENTS v LIST OF FIGURES vii LIST OF TABLES ix Chapter 1 Introduction 1 1.1 Motivation………………………………………………………………………………………………………………………………1 1.2 Thesis Organization………………………………………………………………………………………………………2 Chapter 2 Architecture of The Proposed TRNG 3 2.1 Adaptive Injection-Locked Loop…………………………………………………………………………4 2.2 Noise model of Injection-Locked PLL……………………………………………………………6 Chapter 3 Circuit Implementation and Simulation 9 3.1 Pulse Generaotr…………………………………………………………………………………………………………………9 3.2 Charge Pump……………………………………………………………………………………………………………………………10 3.3 Timing-Adjusted Phase Detector…………………………………………………………………………11 3.4 Low Pass Filter…………………………………………………………………………………………………………………14 3.5 Bootstrapped Voltage-Controlled Oscillator…………………………………………16 3.6 One Oscillator Periodical Constant Delay Divider…………………………21 Chapter 4 Measured Results 24 4.1 Print Circuit Board Design……………………………………………………………………………………24 4.2 Measurement Environment……………………………………………………………………………………………25 4.3 Chip Area and Experiment Setup…………………………………………………………………………26 4.4 Measurement Result…………………………………………………………………………………………………………27 4.5 Comparison………………………………………………………………………………………………………………………………29 Chapter 5 Conclusion and Future Work 31 REFERENCE 32 | |
| dc.language.iso | en | |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | 硬體亂數生成器 | zh_TW |
| dc.subject | TRNG | en |
| dc.subject | Phase-Locked Loop | en |
| dc.title | 利用一個0.5V自動注入鎖相迴路實現硬體亂數生成器 | zh_TW |
| dc.title | A 0.5V Phase-Locked Loop with Adaptive Injection-Locked Technique for True Random Number Generators | en |
| dc.date.schoolyear | 110-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.coadvisor | 趙昌博(Chang-Po Chao) | |
| dc.contributor.oralexamcommittee | 曹恆偉(Hsin-Tsai Liu),(Chih-Yang Tseng) | |
| dc.subject.keyword | 鎖相迴路,硬體亂數生成器, | zh_TW |
| dc.subject.keyword | Phase-Locked Loop,TRNG, | en |
| dc.relation.page | 35 | |
| dc.identifier.doi | 10.6342/NTU202200022 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2022-01-12 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2027-01-14 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| U0001-0601202222442500.pdf 未授權公開取用 | 2.47 MB | Adobe PDF | 檢視/開啟 |
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