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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81861完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭大維(Tei-Wei Kuo) | |
| dc.contributor.author | Chun-Feng Wu | en |
| dc.contributor.author | 吳俊峯 | zh_TW |
| dc.date.accessioned | 2022-11-25T03:05:17Z | - |
| dc.date.available | 2025-06-30 | |
| dc.date.copyright | 2021-08-18 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-06-30 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81861 | - |
| dc.description.abstract | 大數據時代，當DRAM容量無法儲存龐大的資料量時，記憶體與儲存裝置間將產生頻繁的資料搬移。系統運行深度學習或圖論運算這類資料密集型(Data-Intensive)應用時，龐大的資料搬移時間將大幅影響系統效能。儘管購買更大量的DRAM可以減少資料搬移量，然而數據顯示資料的成長速度已經快過單位價格下DRAM容量的成長速度，因此昂貴建置成本漸漸成為消費者的夢魘。非揮發性記憶體的發展逐漸成熟，能以較低的價格提供比DRAM更大的記憶體空間，亦能有效縮短記憶體與儲存裝置間的資料搬移速度，這些優勢使其能以低成本來延伸主記憶體空間。然而，系統中陳舊的記憶體架構以及作業系統設計，使得系統無法直接受惠於非揮發性記憶體快速存取速度的優勢。 在這樣的轉折點，為了能讓系統享受到非揮發性記憶體(NVM)快速的存取速度，本博士論文旨在重新思考以及重新設計整個計算機系統，提供消費者以NVM支援高效大型主記憶體之延伸的解決方案。首先，我們探討使用低價的混合式NVM(亦即在一塊記憶體模組上搭載著高速與低速的記憶體晶片)，容易使當今系統架構面臨Great Memory Wall的議題導致系統效能極不穩定。我們提出了一套協同整合設計來管理CPU以及像是NVDIMM這類混合式NVM，主要在橋接CPU與NVDIMM之間的程式訊息落差，並透過資料預搬移避免Great Memory Wall。接著我們觀察到現今作業系統提供的虛擬記憶體管理單元無法有效利用NVM裝置提供的極低延遲存取速度以及極高的平行度。不同於以往頁管理(Page Management)採用固定的大小，我們提出一套動態頁管理的策略，根據不同時間的程式存取行為選擇合適的頁大小有效利用平行度，並針對不同頁大小我們會採取適合的I/O模式(同步或非同步I/O)藉以利用極低延遲存取速度的優勢。最後，我們更發現當NVM裝置的速度來到數個微秒時，傳統I/O管理層龐大且複雜的優化設計(例如上下文交換)，不僅無法提供優化的效果，反而逐漸成為整個系統效能的瓶頸。在這樣的趨勢下，我們提出一套輕量化的I/O管理設計，重新設計適合現今裝置的機制並將陳舊的優化設計拔除，藉以能使消費者直接享受到由於NVM裝置不斷變快，使記憶體延伸的效能不斷逼近主記憶體效能的優勢。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-25T03:05:17Z (GMT). No. of bitstreams: 1 U0001-2806202116555800.pdf: 5255241 bytes, checksum: 478e4ee1b20cced0ff768b47625799e4 (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | "Abstract in Chinese vii Abstract ix Acknowledgment xi Contents xiii List of Figures xvii List of Tables xviii 1 Introduction 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Background and Related Work . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.1 Trend of Computer Architecture: NVM Technologies. . . . . . .5 1.2.2 Operating Systems: Virtual Memory Management . . . . . . . . 8 1.3 Objectives and Contributions . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Joint Management of CPU and NVDIMM to Break Down the Great Memory wall 13 2.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.1 Background and Great Memory Wall . . . . . . . . . . . . . . . . 13 2.1.2 Motivational Experiment and Observations . . . . . . . . . . . . 15 2.1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2 Joint Management Framework . . . . . . . . . . . . 20 2.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.2 Page Semantic-Aware Strategy . . . . . . . . . . . . . . . . . . . 21 2.2.3 Implementation Remarks: Stall-Aware Process State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.1 Evaluation Metrics and Experiment Setup . . . . . . . . . . . . . 32 2.3.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3 When Storage Response Time Catches Up with Overall Context Switch Overhead, What is Next? 42 3.1 Background, Observation and Motivation . . . . . . . . . . . . 42 3.1.1 Observation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2 Shadow Huge Page Management . . . . . . . . . . . . . . . . . . . . . 48 3.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.2 Shadow Page Promotion . . . . . . . . . . . . . . . . . . . . . 49 3.2.3 Variable-Sized Prefetcher . . . . . . . . . . . . . . . . . . . . 52 3.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3.1 Performance Metrics and Evaluation Setup . . . . . . . . . . . . 55 3.3.2 Evaluation Results . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4 How to Steal CPU Idle Time When Synchronous I/O Mode Becomes Promising 66 4.1 Background, Observation, and Motivation . . . . . . . . . . . . . 66 4.1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.1.2 Observation: CPU Idle Time . . . . . . . . . . . . . . . 68 4.1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.2 Idle-Time-Stealing (ITS) Design . . . . . . . . . . . . . . . . . . . 71 4.2.1 Design Overview Concept . . . . . . . . . . . . . . . . . . 71 4.2.2 Priority-aware Thread Selection Policy . . . . . . . . . . 74 4.2.3 Self-Sacrificing Kernel Thread . . . . . . . . . . . . . . . . . . 75 4.2.4 Self-Improving Kernel Thread . . . . . . . . . . . . . . . . . . 77 4.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . 83 4.3.1 Performance Metrics and Evaluation Setup . . . . . 83 4.3.2 Evaluation Results . . . . . . . . . . . . . . . . . . . . . . . 86 4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5 Concluding Remarks 93 Bibliography 96 Curriculum Vitae 106 Publication List 107 " | |
| dc.language.iso | en | |
| dc.subject | 資料預取 | zh_TW |
| dc.subject | 極低延遲裝置 | zh_TW |
| dc.subject | 非揮發性記體 | zh_TW |
| dc.subject | 虛擬記憶體技術 | zh_TW |
| dc.subject | 記憶體延伸 | zh_TW |
| dc.subject | 頁調換 | zh_TW |
| dc.subject | 非揮發性雙列直插式記憶體模組 | zh_TW |
| dc.subject | 上下文交換 | zh_TW |
| dc.subject | 頁管理 | zh_TW |
| dc.subject | 大頁管理 | zh_TW |
| dc.subject | 同步I/O模式 | zh_TW |
| dc.subject | 記憶體大牆 | zh_TW |
| dc.subject | Great Memory Wall | en |
| dc.subject | Page Swapping | en |
| dc.subject | Huge Page Management | en |
| dc.subject | Main-Memory Extension | en |
| dc.subject | Virtual Memory Management | en |
| dc.subject | Non-Volatile Memory | en |
| dc.subject | Ultra-Low-Latency Devices | en |
| dc.subject | NVDIMM | en |
| dc.subject | Synchronous I/O Mode | en |
| dc.subject | Page Management | en |
| dc.subject | Context Switch | en |
| dc.subject | Data Prefetching | en |
| dc.title | 以非揮發性記憶體支援大型主記憶體之延伸 | zh_TW |
| dc.title | Support to Huge Main-Memory Extension with Non-Volatile Memory | en |
| dc.date.schoolyear | 109-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.author-orcid | 0000-0002-6367-0517 | |
| dc.contributor.advisor-orcid | 郭大維(0000-0003-1974-0394) | |
| dc.contributor.coadvisor | 張原豪(Yuan-Hao Chang) | |
| dc.contributor.coadvisor-orcid | 張原豪(0000-0002-1282-2111) | |
| dc.contributor.oralexamcommittee | 洪士灝(Hsin-Tsai Liu),施吉昇(Chih-Yang Tseng),薛智文,曹昱 | |
| dc.subject.keyword | 記憶體延伸,虛擬記憶體技術,非揮發性記體,極低延遲裝置,非揮發性雙列直插式記憶體模組,記憶體大牆,同步I/O模式,資料預取,上下文交換,頁管理,大頁管理,頁調換, | zh_TW |
| dc.subject.keyword | Main-Memory Extension,Virtual Memory Management,Non-Volatile Memory,Ultra-Low-Latency Devices,NVDIMM,Great Memory Wall,Synchronous I/O Mode,Data Prefetching,Context Switch,Page Management,Huge Page Management,Page Swapping, | en |
| dc.relation.page | 112 | |
| dc.identifier.doi | 10.6342/NTU202101173 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2021-07-01 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2025-06-30 | - |
| 顯示於系所單位： | 資訊工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| U0001-2806202116555800.pdf | 5.13 MB | Adobe PDF | 檢視/開啟 |
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