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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81720完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
| dc.contributor.author | Da-Wei Lin | en |
| dc.contributor.author | 林大瑋 | zh_TW |
| dc.date.accessioned | 2022-11-24T09:26:14Z | - |
| dc.date.available | 2022-11-24T09:26:14Z | - |
| dc.date.copyright | 2022-01-17 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-12-24 | |
| dc.identifier.citation | [1] Fengyi Mei, Yujun Shu and Youling Yu School of electronics and Information Engineering, Tong University Shanghai, China” A 10-bit 150MS/s SAR ADC with a Novel Capacitor Switching Scheme, ” in 3rd IEEE International Conference on 'Computational Intelligence and Communication Technology' (IEEE-CICT 2017) [2] Chun-Cheng Liu, Student Member, IEEE, Soon-Jyh Chang, Member, IEEE, Guan-Ying Huang, Student Member, IEEE, and Ying-Zu Lin, Student Member, IEEE, ”A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 [3] C. Liu,C. Kuo and Y. Lin,”A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS,” in IEEE Journal of Solid-State Circuits,vol. 50,no. 11, pp. 2645-2654, Nov.2015 [4] Jianfeng Xue , Hanie Ghaedrahmati, Jing Jin,” A 10-bit 160MS/s SAR ADC with Fast-Response Reference Voltage Buffer ,” Center for Analog/RF Integrated Circuit (CARFIC), School of Electronic Information and Electrical Engineering Shanghai Jiao Tong University, Shanghai 200240, China in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) [5] Yung-Hui Chung; Hsuan-Chih Yeh; Che-Wei Chang Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan,” A 10b 160-MS/s domino-SAR ADC in 90nm CMOS,” in 2018 7th International Symposium on Next Generation Electronics (ISNE) [6] DaiguoXu ,Hequan Jiang, Lei Qiu , Xiaoquan Yu, Jianan Wang, Zhengping Zhang, Can Zhu, and Shiliu Xu,” A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique,”in IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 9, SEPTEMBER 2019 [7] Johannes Digel,Markus Grozing and Manfred Berroth,”A 10 bit 90MS/s SAR ADC in 65nm CMOS Technology,” in 2016 IEEE Institute of Electrical and Optical Communications Engineering, University of Stuttgart, Germany [8] Ayca Akkaya; Firat Celik ; Yusuf Leblebici, ”A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS,” in 2020 IEEE International Symposium on Circuits and Systems (ISCAS) [9] Tomohiko Ogawa, Haruo Kobayashi, Masao Hotta Yosuke Takahashi, Hao San and Nobukazu Takai, ” SAR ADC Algorithm with Redundancy,” APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems [10] Guan-Ying Huang, Soon-Jyh Chang, Ying-Zu Lin, Chun-Cheng Liu and Chun-Po Huang, “A 10 b 200 MS/s 0.82 mW SAR ADC in 40nm CMOS,” in 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) [11] Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, and Ying-Zu Lin, “10-bit 30 MS/s SAR ADC using a switchingback switching method,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Volume: 21, Issue: 3, March 2013) | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81720 | - |
| dc.description.abstract | 本論文提出三個應用於逐漸趨近式類比數位轉換器的電路設計技術，並且基於所提出的技術實現一個使用九十奈米製程的單通道十位元每秒取樣兩億兩千萬次的非同步逐漸趨近式類比數位轉換器。第一個技術為加倍分解MSB電容法，此技術為將MSB電容拆成四等分，以降低MSB電容的充、放電時間，進而讓DAC電壓更快穩定，使動態比較器可以越快開始比較，進而降低ADC的轉換時間，以提升ADC的取樣率，此外，使用這個方法電容在切換時其正端電容上板電壓和負端電容上板電壓的平均值相對其他沒有使用這個方法的正端負端電容上板電壓的平均值，此方法的正端負端電容上板電壓平均值的變動較小，因此比較器的動態偏移會變小。第二個技術為改善動態比較器的架構，使動態比較器的比較速度更快，進而提升ADC的取樣率。第三個技術為改善的數位控制電路，用來更快地對比較器進行重置和開啟比較，使ADC的取樣率上升。 本設計使用台積電90-nm UTM CMOS製程來製作晶片，其核心面積約為0.023mm2。佈局後模擬結果顯示，此設計在電源供應電壓為1伏特時與取樣率220MS/s的情況下，總消耗功率為1.93mW，有效位元為9.9068 bits，每次資料轉換所消耗的能量為9.14fJ。DNL 與INL分別為 +0.098/-0.432 LSB與 +0.252/-0.304 LSB。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-24T09:26:14Z (GMT). No. of bitstreams: 1 U0001-2212202111232100.pdf: 4232616 bytes, checksum: b4da42cc382bd88517b12ed131c012fb (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | 口試委員審定書 i 誌謝 ii 中文摘要 iii ABSTRACT iiii CONTENTS vi LIST OF FIGURES x LIST OF TABLES xiv Chapter 1 Introduction ...1 1.1 Motivation ...1 1.2 Organization of the thesis ...3 Chapter 2 Rudiments of Analog-to-Digital Converter ...4 2.1 Basic Concept of ADCs ...4 2.2 Quantization Error ...5 2.3 Static Specifications ...8 2.3.1 Offset Error ...8 2.3.2 Gain Error ...9 2.3.3 Differential Non-Linearity (DNL) ...10 2.3.4 Integral Non-Linearity (INL) ...12 2.4 Dynamic Specifications ...15 2.4.1 Signal-to-Noise Ratio (SNR) ...16 2.4.2 Signal-to-Noise and Distortion Ratio (SNDR) ...17 2.4.3 Spurious-Free Dynamic Range (SFDR) ...17 2.4.4 Effective Number-Of-Bits (ENOB) ...18 2.4.5 Effective Resolution Bandwidth (ERBW) ...18 2.4.6 Total Harmonic Distortion (THD) ...18 Chapter 3 Architectures of Different types of Analog-to-Digital Converters ...19 3.1 Flash ADC ...19 3.2 Pipelined ADC ...22 3.3 Successive-Approximation (SAR) ADC ...24 Chapter 4 The Proposed 10-bit 220-MS/s SAR ADC ...26 4.1 Abstract ...26 4.2 The Proposed Techniques ....28 4.2.1 Proposed Double Split-MSB Capacitor Method ...28 4.2.2 Proposed Dynamic Comparator ...32 4.2.3 Proposed Digital Control Circuits ...35 4.3 Architecture of the Proposed SAR ADC ...39 4.3.1 Bootstrapped Switch ...41 4.3.2 Non-Binary Capacitive DAC ...42 4.3.3 Sampling Clock Generator ...43 4.3.4 Proposed Digital Control Circuits ...45 4.3.5 Proposed Dynamic Comparator ...45 4.3.6 DAC Control Logic Circuits With Latch Cells ...46 4.3.7 Bit Error Correction Decoder ....47 Chapter 5 Post-layout Simulations and Measurement Results ...49 5.1 Chip Layout ...49 5.2 Post-layout Simulations ...50 5.2.1 The Dynamic Performance Of The Proposed ADC Under Process Variation ...50 5.2.2 The Dynamic Performance Of The Proposed ADC Under Supply Voltage Variation ...54 5.2.3 The Dynamic Performance Of The Proposed ADC Under Temperature Variation ...56 5.2.4 The Static Performance Of The Proposed ADC ...59 5.3 PCB and Die Micrograph and Chip Layout ...60 5.4 Measurement Setup and Measurement Results ...62 Chapter 6 Conclusions and Future Work ...67 REFERENCES ...69 | |
| dc.language.iso | en | |
| dc.subject | 改善的數位控制電路 | zh_TW |
| dc.subject | 逐漸趨近式類比數位轉換器 | zh_TW |
| dc.subject | 九十奈米製程 | zh_TW |
| dc.subject | 加倍分解MSB電容法 | zh_TW |
| dc.subject | 改善動態比較器 | zh_TW |
| dc.subject | speed-enhanced dynamic comparator | en |
| dc.subject | improved digital control circuits | en |
| dc.subject | successive-approximation (SAR) analog-to-digital converters(ADCs) | en |
| dc.subject | 90-nm CMOS process | en |
| dc.subject | double split-MSB capacitor method | en |
| dc.title | 一個使用三個提升速度的方法之九十奈米十位元每秒取樣兩億兩千萬次的逐漸趨近式類比數位轉換器 | zh_TW |
| dc.title | A 10-bit 220-MS/s SAR ADC with Three Methods to Enhance Speed in 90nm CMOS Technology | en |
| dc.date.schoolyear | 110-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳巍仁(Hsin-Tsai Liu),陳新(Chih-Yang Tseng),林明郎 | |
| dc.subject.keyword | 逐漸趨近式類比數位轉換器,九十奈米製程,加倍分解MSB電容法,改善動態比較器,改善的數位控制電路, | zh_TW |
| dc.subject.keyword | successive-approximation (SAR) analog-to-digital converters(ADCs),90-nm CMOS process,double split-MSB capacitor method,speed-enhanced dynamic comparator,improved digital control circuits, | en |
| dc.relation.page | 71 | |
| dc.identifier.doi | 10.6342/NTU202104554 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2021-12-24 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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