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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 王暉(Huei Wang) | |
dc.contributor.author | Xin-Yi Li | en |
dc.contributor.author | 黎欣怡 | zh_TW |
dc.date.accessioned | 2021-05-20T00:49:17Z | - |
dc.date.available | 2025-08-18 | |
dc.date.available | 2021-05-20T00:49:17Z | - |
dc.date.copyright | 2020-08-24 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-08-18 | |
dc.identifier.citation | REFERENCE
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8147 | - |
dc.description.abstract | 本論文提出一個高線性度和高效率38-GHz功率放大器,一個38-GHz I/Q混頻器,以及一個由上述兩個元件所組成之38-GHz發射器。 在第二章,使用65奈米金氧半場效電晶體製程實現一個高線性度和高效率38-GHz功率放大器應用於第五代通訊系統,為了改善回推效率,前級放大器為深度AB類操作. 輸出級匹配電路損耗只有1 dB,達到高效率之結果。設計兩級共源極功率放大器,以提供足夠增益。使用中和技術(Neutralization),改善穩定度並且提升增益。此功率放大器在38-GHz達到了20.5-dB之小訊號增益,14.6-dBm之大訊號飽和輸出功率,35.8%的最大功率附加效率,在1-dB壓縮點有13.1-dBm之輸出功率和30.1%之功率附加效率。線性度測試在EVM為-25 dB的條件下能有10.1 dBm的輸出功率與17%的功率附加效率。 在第三章,使用65奈米金氧半場效電晶體製程實現一個高鏡像抑制率I/Q混頻器。採用Gilbert-cell混頻器在I/Q路徑上,中頻端串接上反向緩衝器(inverter type buffer) 提升轉換增益並且利用本身的阻抗達到低頻匹配的效果,以實現直接轉換(direct conversion)。為了實現高速傳輸,在晶片上設計精準四相位訊號產生器以降低I/Q不平衡。此I/Q混頻器的量測結果在37-GHz達到了4.3 dB之轉換增益,54.7 dB之鏡像拒斥比,46.8 dB之本地振盪洩漏(LO Leakage)。調變訊號量測結果顯示此混頻器在高階正交振幅調變(QAM)下,最高可傳輸之資料速率為2.4 Gb/s。 最後部分是關於一個38-GHz 發射器的整合與量測,此發射器由I/Q混頻器在輸出端接上功率放大器組成,在先前兩個章節,第二章與第三章分別詳細介紹了功率放大器與I/Q混頻器。此發射機的量測結果在38-GHz達到了25.8-dB之轉換增益,11.6-dBm之1-dB壓縮點輸出功率,29.3-dB之鏡像拒斥比,34.8-dB之本地振盪洩漏。此發射機的直流功耗105mW,晶片面積為0.9184 mm2。調變訊號量測結果顯示此發射機在高階正交振幅調變(QAM)下,最高傳輸之資料速率為2.1 Gb/s。 | zh_TW |
dc.description.abstract | In this thesis, a 38-GHz power amplifier (PA), a Ka-band I/Q mixer, and a 38-GHz transmitter are proposed. In chapter 2, a 38-GHz high linearity and high efficiency power amplifier is proposed for 5G applications in 65-nm CMOS. To improve the back-off efficiency, transistors of the driver stage are biased in deep class-AB. Insertion loss from output stage matching is only 1 dB, resulting in high efficiency. A two-stage common source PA is designed to provide enough gain. Neutralization technique is applied to improve the stability and boost the power gain. This PA achieves a 20.5-dB small-signal gain, 14.6-dBm PSAT, 35.8% peak power-added efficiency (PAE), 13.1-dBm P1dB, and 30.1% PAE1dB. The linearity measured in error vector magnitude (EVM) is better than -25 dB, with a 10.1-dBm output power and 17% PAE. In chapter 3, a Ka-band high image reject ratio I/Q mixer using 65-nm CMOS process is presented. Gilbert-cell mixer is applied on the I/Q path. In order to improve the conversion gain and realized the impedance matching at low frequency, inverter type buffer is used at the IF port. To demonstrate high data rate transmission, an on-chip accuracy quadrature signal generator is designed to reduce the I/Q imbalance. This I/Q mixer achieves 4.3-dB conversion gain, 54.7-dBc image reject ratio, 46.8-dB LO leakage at 37-GHz. In digital modulation measurement, this I/Q mixer can support data rate 2.4 Gb/s transmission under 64-quadrature amplitude modulation (64-QAM). The last part is integration and measurement of a 38 GHz transmitter system. System circuits are fabricated in 65-nm CMOS technology. The detail of power amplifier and I/Q mixer is discussed in chapter 2 and 3. The measurement result shows that the transmitter achieves 25.8-dB conversion gain, 11.6-dBm output power at 1-dB compression, 29.4-dB IRR, and 34.8-dB LO leakage. The dc power is 105 mW and the chip size is 0.9184 mm2. | en |
dc.description.provenance | Made available in DSpace on 2021-05-20T00:49:17Z (GMT). No. of bitstreams: 1 U0001-1708202021065200.pdf: 8326215 bytes, checksum: 4e4e57156da074e591cdb0cf8ae6c537 (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | 口試委員會審定書 # 誌謝 i 中文摘要 ii ABSTRACT iv CONTENTS vi LIST OF FIGURES ix LIST OF TABLES xvii Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Literature Survey 2 1.2.1 Ka-band Power Amplifier 2 1.2.2 Up-conversion Mixer 3 1.2.3 Transmitter 6 1.3 Contributions 7 1.3.1 38-GHz-band Power Amplifier 7 1.3.2 Ka-band I/Q Mixer 7 1.3.3 38-GHz-band Transmitter 8 1.4 Thesis Organization 8 Chapter 2 Design of a 38-GHz High Linearity and High Efficiency Power Amplifier in 65-nm CMOS Technology 9 2.1 Introduction 9 2.2 Circuit Design 10 2.2.1 Device Selections and Matching Network Designs 11 2.2.2 Linearity Enhancement 31 2.2.3 Simulation Results 34 2.3 Experimental Results 38 2.4 Summary 46 Chapter 3 Design of a Ka-band High Image Reject I/Q Mixer in 65-nm CMOS Technology 48 3.1 Introduction 49 3.1.1 Single Sideband Mixer [39] 49 3.1.2 Image Rejection Ratio 50 3.2 Circuit Design 53 3.2.1 Gilbert-cell Mixer 53 3.2.2 Quadrature Signal Generator 59 3.2.3 Output Transformer 67 3.2.4 Simulation Results 70 3.3 Experimental Result 73 3.4 Summary 84 Chapter 4 Design of a 38-GHz Direct-Conversion Transmitter in 65-nm CMOS Technology for 5G Applications 86 4.1 Introduction 86 4.2 Circuit Design 86 4.2.1 Direct-Conversion Transmitter Design 86 4.2.2 Simulation Results 88 4.3 Experimental Results 91 4.4 Summary 98 Chapter 5 Conclusion 100 REFERENCE 102 | |
dc.language.iso | en | |
dc.title | 應用於第五代通訊之功率放大器與正交混頻器之設計 | zh_TW |
dc.title | Design of Power Amplifier and I/Q Mixer for 5G Communications | en |
dc.type | Thesis | |
dc.date.schoolyear | 108-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃天偉(Tian-Wei Huang),林坤佑(Kun-You Lin),蔡作敏(Zuo-Min Tias),張鴻埜 | |
dc.subject.keyword | 功率放大器,正交混頻器,鏡像抑制率,發射器,第五代通訊,互補式金氧半場效電晶體, | zh_TW |
dc.subject.keyword | power amplifier,I/Q mixer,image rejection ratio,transmitter,5G communications,CMOS, | en |
dc.relation.page | 108 | |
dc.identifier.doi | 10.6342/NTU202003867 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2020-08-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
dc.date.embargo-lift | 2025-08-18 | - |
顯示於系所單位: | 電信工程學研究所 |
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