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請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81363
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor王暉(Huei Wang)
dc.contributor.authorTzu-Yang Chiuen
dc.contributor.author邱梓洋zh_TW
dc.date.accessioned2022-11-24T03:45:36Z-
dc.date.available2021-07-20
dc.date.available2022-11-24T03:45:36Z-
dc.date.copyright2021-07-20
dc.date.issued2021
dc.date.submitted2021-07-14
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81363-
dc.description.abstract本論文提出了三個應用於微波及毫米波系統的關鍵放大器,其所使用的製程皆為90奈米互補式金氧半電晶體(CMOS FET)製程,第一個為低功耗且小晶片面積的高增益寬頻可變增益分散式放大器。第二個為創新且晶片核心面積小的變壓器匹配之無開關雙向功率低雜訊放大器。最後一個為應用於E頻帶的可變增益低雜訊放大器。 首先提出的放大器以混和傳統分散式放大器(CDA)以及串接單級分散式放大器(CSSDA)為架構,並以疊接放大器(cascode amplifier)為其中的增益元件,再利用主動終端可變電阻(AVTR)來達到平坦增益度之可變增益分散式放大器。其中增益頻寬積(GBW product)、直流功耗、增益控制範圍以及晶片面積為此可變增益分散式放大器的重要考量。在利用主動終端可變電阻的情形下,其增益平坦度可以做到有效的調整,且不會有增加直流功耗以及占用晶片面積之問題。此可變增益分散放大器達到21 dB的小訊號增益、40 GHz的3-dB頻寬以及18 dB的增益控制範圍,且直流功耗在最高的增益狀態僅有32.9 mW,而晶片的總面積只有0.72平方毫米。 接著是設計於Ka頻段基於變壓器架構之無開關雙向功率低雜訊放大器(switchless bidirectional PA-LNA),其採用了創新的雙向變壓器匹配網路來達到虛擬開關(virtual switch)之效果,以取代傳統的單刀雙擲開關(SPDT switch)電路,如此一來不僅能保有功率放大器以及低雜訊放大器原有之特性,還可以達到節省晶片面積之效果。此功率低雜訊放大器在功率放大器模式下達到18.1 dB的小訊號增益、9.5 GHz的3-dB頻寬以及在33 GHz的操作頻率下達到15.2 dBm的飽和輸出功率、29 %之最高功率附加效率。在低雜訊放大器模式下達到18.1 dB的小訊號增益、4.2 GHz的3-dB頻寬以及在35 GHz的操作頻率下達到最小4.5 dB的雜訊指數,而在3-dB頻寬下達到4.8 dB的平均雜訊指數。此晶片的核心面積只有0.21平方毫米。 最後提出的是應用於E頻段的可調增益低雜訊放大器,其電路由兩級的電流再利用(current-reused)架構串聯一級疊接放大器以及一級電流導引(current-steering)結構的放大器所組合而成。其中小訊號增益、直流功耗以及增益調控範圍為設計此放大器之考量。利用電流共享架構以及增益增強技術,此可調增益低雜訊放大器可以達到26.1 dB的小訊號增益和14.1 GHz的3-dB頻寬,在78 GHz的操作頻率下達到最小4.8 dB的雜訊指數以及17 dB的增益控制範圍,而在3-dB頻寬下達到5.4 dB的平均雜訊指數。此外其直流功率僅消耗23 mW且此晶片的整體面積只有0.52平方毫米。zh_TW
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dc.description.tableofcontents誌謝 i 中文摘要 ii ABSTRACT iv CONTENTS vi LIST OF FIGURES x LIST OF TABLES xix Chapter 1 Introduction 1 1.1 Backgrounds and Motivations 1 1.2 Literature Survey 4 1.2.1 Wideband VGAs 4 1.2.2 Switchless bidirectional PA-LNAs 5 1.2.3 High-Frequency LNAs and VG-LNAs 7 1.3 Contributions 9 1.3.1 Ultra-Wideband VGDA 9 1.3.2 Switchless Bidirectional PA-LNA 9 1.3.3 E-band High Gain VG-LNA 10 1.4 Thesis Organization 11 Chapter 2 Design of a Variable Gain Distributed Amplifier with Low Power Consumption in 90-nm CMOS Process 12 2.1 Classification of Distributed Amplifier Architecture 13 2.1.1 Conventional Distributed Amplifier [37] 13 2.1.2 Cascaded Single-Stage Distributed Amplifier [40] 15 2.1.3 Cascaded Multi-Stage Distributed Amplifier [41] 17 2.1.4 Matrix Distributed Amplifier [42] 18 2.1.5 Distributed Amplifier with Cascaded Gain Stages [38] 20 2.1.6 Distributed Amplifier with Internal Feedback [43] 21 2.2 Techniques of Distributed Amplifiers for Performance Enhancement 23 2.2.1 Configurations of Unit Gain Cell 23 2.2.2 Capacitive Division Technique [37] 25 2.2.3 M-Derived Technique [45] [46] 27 2.2.4 Inter-stage Termination Removed Technique [47] 29 2.3 Design of Proposed Variable Gain Distributed Amplifier [33] 30 2.3.1 Basic Circuit Concept 30 2.3.2 Device Size and Bias Selections 32 2.3.3 Design of CDA Stage 35 2.3.4 Design of CSSDA Stage 40 2.3.5 Active Variable Termination Resistor [77] 42 2.3.6 Complete Circuit Schematic and Simulation Results 47 2.4 Experimental Results 53 2.5 Summary 60 Chapter 3 Design of a Ka-band Transformer-Based Switchless Bidirectional PA-LNA in 90-nm CMOS Process [34] 62 3.1 Phased-Array System [5]-[7] 63 3.2 Design Concepts of PA-LNA 65 3.2.1 Amplifier Structure of PA and LNA cores 65 3.2.2 Bidirectional Matching Network 67 3.2.3 PA-LNA Design Trades 68 3.3 Design of PA 72 3.3.1 Block Diagram and Power Budget 72 3.3.2 Device and Bias Selection 72 3.3.3 Driver Stage Design 76 3.3.4 Capacitive Neutralization Technique 77 3.3.5 Matching Networks 80 3.3.6 Circuit Schematic and OFF-state Impedance Check 83 3.4 Design of LNA 85 3.4.1 Matching Network 86 3.4.2 OFF-state Impedance Check 90 3.5 Complete Switchless Bidirectional PA-LNA 93 3.6 Simulated Results of PA-LNA 95 3.7 Fabrication and Experimental Results 102 3.7.1 Digital Modulation 110 3.8 Method to Deal with Common Mode Oscillation of RFIC [63] [78] 114 3.8.1 Common Mode Stability Analysis 114 3.8.2 Common Mode Oscillation Experiment and Debugging 117 3.9 Summary 124 Chapter 4 Design of an E-band Variable Gain Low Nosie Amplifier with High Gain and Low-Power Dissipation in 90-nm CMOS Process 125 4.1 Design Concepts 126 4.1.1 Noise Reduction Technique [64] 127 4.1.2 Gm-Boosting Technique [65] 131 4.1.3 Body-Floating Technique [16] 133 4.1.4 Current-Reused Topology [66] 136 4.1.5 Current-Steering Topology [71] 137 4.2 Circuit Implementation of the E-band VG-LNA 140 4.3 Fabrication and Experimental Results 146 4.4 Summary 153 Chapter 5 Conclusions 155 REFERENCES 157
dc.language.isoen
dc.subject寬頻放大器zh_TW
dc.subject互補式金屬氧化物製程zh_TW
dc.subject低雜訊放大器zh_TW
dc.subject無開關雙向放大器zh_TW
dc.subjectKa頻段zh_TW
dc.subject單刀雙擲開關zh_TW
dc.subjectE頻段zh_TW
dc.subject功率放大器zh_TW
dc.subject可變增益放大器zh_TW
dc.subject變壓器匹配網路zh_TW
dc.subject線性電阻zh_TW
dc.subject分散式放大器zh_TW
dc.subjectbroadband amplifieren
dc.subjectKa-banden
dc.subjectCMOSen
dc.subjectdistributed amplifieren
dc.subjectlinear resistoren
dc.subjecttransformer matching networken
dc.subjectpower amplifieren
dc.subjectlow noise amplifieren
dc.subjectswitchless bidirectional amplifieren
dc.subjectSPDT switchen
dc.subjectE-banden
dc.subjectvariable gain amplifieren
dc.title超寬頻且低功耗的可變增益分散式放大器與毫米波放大器之研究zh_TW
dc.titleResearches on Ultra-Wideband Low-Power Consumption Variable Gain Distributed Amplifier and Millimeter-Wave Amplifiersen
dc.date.schoolyear109-2
dc.description.degree碩士
dc.contributor.oralexamcommittee黃天偉(Hsin-Tsai Liu),林坤佑(Chih-Yang Tseng),蔡作敏,蔡政翰
dc.subject.keyword互補式金屬氧化物製程,寬頻放大器,分散式放大器,線性電阻,變壓器匹配網路,功率放大器,低雜訊放大器,無開關雙向放大器,Ka頻段,單刀雙擲開關,E頻段,可變增益放大器,zh_TW
dc.subject.keywordCMOS,broadband amplifier,distributed amplifier,linear resistor,transformer matching network,power amplifier,low noise amplifier,switchless bidirectional amplifier,Ka-band,SPDT switch,E-band,variable gain amplifier,en
dc.relation.page164
dc.identifier.doi10.6342/NTU202101454
dc.rights.note同意授權(限校園內公開)
dc.date.accepted2021-07-14
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電信工程學研究所zh_TW
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