請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8096| 標題: | 氣隙置入結合繞線層重新分配於電路時序最佳化之應用 Circuit Timing Optimization by Airgap Insertion with Layer Reassignment |
| 作者: | Yu-Cheng Lin 林禹丞 |
| 指導教授: | 江蕙如(Iris Hui-Ru Jiang) |
| 關鍵字: | 氣隙,繞線層重新分配,時序最佳化, airgap,layer reassignment,timing optimization, |
| 出版年 : | 2020 |
| 學位: | 碩士 |
| 摘要: | 氣隙是藉由在導線間的金屬導線間介電層形成空隙來降低導線電容的技術。由於氣隙的形成需要高昂的成本,因此能夠置入氣隙的繞線層(氣隙繞線層)之數量是有限制的。基於導線電容的下降,氣隙可以用來優化電路時序,但優化後不能產生任何保持時間(hold time)違例。為了在有限的氣隙繞線層中置入氣隙,有兩個問題必須被處理。分別是繞線層重新分配與氣隙置入。前者會決定每個導線片段所在的繞線層,將導線片段移至氣隙繞線層或從氣隙繞線層移走。後者會決定每個在氣隙繞線層的導線片段之氣隙置入量。在這篇論文中,我們提出了一個方法來處理這兩個問題以最小化建立時間(setup time)違反總量,同時不產生任何保持時間違例。我們提出一個以網路流為基礎的氣隙置入方法,在決定一個導線片段的氣隙置入量時會考慮部分的氣隙置入量,並能在大多數情況下對一個固定繞線層分配的連線找到氣隙置入的最佳解。實驗結果顯示我們的方法與先前的方法相比,達成稍微更多的建立時間改善僅需要約24%的執行時間。 Airgap is a technique to reduce interconnect capacitance by forming voids in inter-metal dielectrics (IMD) between interconnects. The number of layers that can insert airgap (airgap layers) is limited because of the high cost of airgap formation. With the utilization of airgap, circuit timing can be optimized due to the reduction of interconnect capacitance. However, hold time violations are not allowed after airgap insertion. In order to insert airgap with limited airgap layers, two problems need to be addressed. They are layer reassignment and airgap insertion. The former determines the layer of each wire segment. It can move wire segments to or from airgap layers. The latter determines the amount of airgap inserted to each wire segment in airgap layers. In this thesis, we propose a method to cope with these two problems for minimizing setup total negative slack (TNS) without generating hold time violations. We propose a network flow based airgap insertion method, which considers partial airgap for inserting airgap to a wire segment and finds an optimal solution for the airgap insertion of a setup timing critical net with fixed layer assignment in most cases. Experimental results show that our method can achieve slightly more setup TNS improvement with only about 24% runtime in comparison with the method of a previous work. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8096 |
| DOI: | 10.6342/NTU202004262 |
| 全文授權: | 同意授權(全球公開) |
| 電子全文公開日期: | 2025-10-15 |
| 顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| U0001-1410202007254000.pdf | 2.67 MB | Adobe PDF | 檢視/開啟 |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。
