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| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
| dc.contributor.author | Jen-Hao Chen | en |
| dc.contributor.author | 陳人豪 | zh_TW |
| dc.date.accessioned | 2022-11-24T03:03:06Z | - |
| dc.date.available | 2021-08-04 | |
| dc.date.available | 2022-11-24T03:03:06Z | - |
| dc.date.copyright | 2021-08-04 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-07-25 | |
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Wu, “Memory Characteristics of Au Nanocrystals Embedded in Metal–Oxide–Semiconductor Structure by Using Atomic-Layer-Deposited Al2O3 as Control Oxide,” J. Phys. D: Appl. Phys., vol. 40, no. 6, pp. 1673-1677, Mar. 2007. [6] W. C. Chen, C. F. Yang and J. G. Hwu, “Enhanced Two States Current in MOS-Gated MIS Separate Write/Read Storage Device by Oxide Soft Breakdown in Remote Gate,” IEEE Trans Nanotechnol, vol. 18, pp. 62-67, Nov. 2018. [7] J. X. Chen, Z. W. Wang, J. H. Cao, D. R. Yang and X. Y. Ma, “Evolution from Random Lasing to Erbium-Related Electroluminescence from Metal-Insulator-Semiconductor Structured Light-Emitting Device with Erbium-Doped ZnO Film on Silicon,” J. Appl. Phys., vol. 127, no. 5, pp. 055705, Feb. 2020. [8] G. R. Lin and C. J. Lin, “Improved Blue-Green Electroluminescence of Metal-Oxide-Semiconductor Diode Fabricated on Multirecipe Si-Implanted and Annealed SiO2 / Si Substrate,” J. Appl. Phys., vol. 95, no. 12, pp. 8484-8486, Jun. 2004. [9] S. Q. Xiao, H. Wang, Z. C. Zhao, Y. Z. Gu, Y. X. Xia and Z. H. Wang, “Lateral Photovoltaic Effect and Magnetoresistance Observed in Co–SiO2–Si Metal–Oxide–Semiconductor Structures,” J. Phys. D: Appl. Phys., vol. 40, no. 22, pp. 6926-6929, Nov. 2007. [10] C. C. Lin, P. L. Hsu, L. Lin and J. G. Hwu, “Investigation on Edge Fringing Effect and Oxide Thickness Dependence of Inversion Current in MOS Tunneling Diodes with Comb-Shaped Electrodes,” J. Appl. Phys., vol. 115, no. 12, pp. 124109, Mar. 2014. [11] Y. K. Lin and J. G. Hwu, “Photosensing by Edge Schottky Barrier Height Modulation Induced by Lateral Diffusion Current in MOS(p) Photodiode,” IEEE Trans. Electron Devices, vol. 61, no. 9, pp.3217-3222, Sep. 2014. [12] C. Y. Yang and J. G. Hwu, “Photo-Sensitivity Enhancement of HfO2-Based MOS Photodiode with Specific Perimeter Dependency due to Edge Fringing Field Effect,” IEEE Sens. J., vol. 12, no. 6, pp. 2313-2319, Jun. 2012. [13] C. S. Liao and J. G. Hwu, “Subthreshold Swing Reduction by Double Exponential Control Mechanism in an MOS Gated-MIS Tunnel Transistor,” IEEE Trans. Electron Devices, vol. 62, no. 6, pp. 2061-2065, Jun. 2015. [14] C. F. Yang, P. J. Chen, W. C. Chen, K. W. Lin and J. G. Hwu, “Gate Oxide Local Thinning Mechanism Induced Sub-60 mV/decade Subthreshold Swing on Charge-Coupled MIS(p) Tunnel Transistor,” IEEE Trans. Electron Devices, vol. 66, no. 1, pp. 279-285, Jan. 2019. [15] T. M. Wang, C. H. Chang and J. G. Hwu, “Enhancement of Temperature Sensitivity of Metal-Oxide-Semiconductor (MOS) Tunneling Temperature Sensors by Utilizing Hafnium Oxide (HfO2) Film Added on Silicon Dioxide (SiO2),” IEEE Sens. J., vol. 6, no. 6, pp. 1468-1472, Dec. 2006. [16] M. G. Hönnicke and C. Cusatis, “X-ray Diffraction Imaging Self-Detected with a CCD,” J. Phys. D: Appl. Phys., vol. 38, no. 10A, pp. A73-A77, May. 2005. [17] S. L. Xu, S. L. Zou and Y. J. Huang, “γ-ray Detection Using Commercial Off-the-Shelf CMOS and CCD Image Sensors,” IEEE Sens. J., vol. 17, no. 20, pp. 6599-6604, Oct. 2017. [18] R. S. Prabhakara, C. H. G. Wright and S. F. Barrett, “Motion Detection: a Biomimetic Vision Sensor versus a CCD Camera Sensor,” IEEE Sens. J., vol. 12, no. 2, pp. 298-307, Feb. 2012. [19] N. Becher, M. Farzaneh, B. Knipfer, C. Sigler, J. Kirch, C. Boyle, D. Botez, L. J. Mawst, D. F. Lindberg III and T. Earles, “Thermal Imaging of Buried Heterostructure Quantum Cascade Lasers (QCLs) and QCL Arrays Using CCD-Based Thermoreflectance Microscopy,” J. Appl. Phys., vol. 125, no. 3, pp. 033102, Jan. 2019. [20] C. S. Liao and J. G. Hwu, “Current Coupling Effect in MIS Tunnel Diode with Coupled Open-Gated MIS Structure,” ECS Trans, vol. 75, no. 5, pp. 77~86, Oct. 2016. [21] Y. K. Yeow and Z. Abbas, “Fringing Field Correction of Admittance Model for Open-Ended Coaxial Sensor,” IEEE Sens. J., vol. 12, no. 5, pp. 1468-1469, May. 2012. [22] T. Ernst, C. Tinella, C. Raynaud and S. Cristoloveanu, “Fringing Fields in Sub-0.1 μm Fully Depleted SOI MOSFETs: Optimization of the Device Architecture,” Solid State Electron., vol. 46, no. 3, pp. 373-378, Mar. 2002. [23] D. Pattanayak, J. Poksheva, R. Downing and L. Akers, “Fringing Field Effect in MOS Devices,” IEEE Trans. Components, Hybrids Manuf. Technol., vol. 5, no. 1, pp. 127-131, Mar. 1982. [24] P. F. Schmidt, and W. Michael, “Anodic Formation of Oxide Films on Silicon,” J. Electrochem. Soc., vol. 104, no. 4, pp. 230-236, Apr. 1957. [25] S. K. Ghandhi, VLSI Fabrication Principle, 2nd ed., Wiley-Interscience, pp. 487-495, 1994. [26] K. J. Yang, and C. Hu, “MOS Capacitance Measurement for High-Leakage Thin Dielectrics,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1500-1501, Jul. 1999. [27] H. W. Lu, T. U. Chen, and J. G. Hwu, “A Novel Methodology to Extract Ultra-thin Dielectric Thickness (<1.8nm) by Analyzing Current Behavior at Oxide Flat-band Voltage,” International Electronic Devices and Materials Symposia - IEDMS 2010, Paper No. D4-6., Kuva Chateau, Chung Li, Taiwan, ROC, Nov. 2010. [28] C. S. Liao, W. C. Kao, and J. G. Hwu, “Energy-Saving Write/Read Operation of Memory Cell by Using Separated Storage Device and Remote Reading with an MIS Tunnel Diode Sensor,” IEEE J. Electron Devices Soc., vol. 4, no. 6, pp. 424~429, Nov. 2016. [29] J. Y. Cheng, C. T. Huang, and J. G. Hwu, “Comprehensive Study on the Deep Depletion Capacitance-Voltage Behavior for Metal-Oxide-Semiconductor Capacitor with Ultra-Thin Oxides,” J. Appl. Phys., vol. 106, no. 7, pp. 074507, Oct. 2009. [30] Y. H. Chen and J. G. Hwu, “Light Sensing Enhancement and Energy Saving Improvement in Concentric Double MIS(p) Tunnel Diode Structure with Inner Gate Outer Sensor (IGOS) Operation,” IEEE Trans. Electron Devices, vol. 65, no. 11, pp. 4910~4915, Nov. 2018. [31] C. S. Liao, “Study of Laterally Gated Metal-Insulator-Semiconductor Tunnel Diode with Al/SiO2/Si(p) Structure and Its Application,” Ph.D. Dissertation Dept. Elect. Eng. Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2017. [32] T. Oya, T. Asai, T. Fukui and Y. Amemiya, “A Majority-Logic Device Using an Irreversible Single-Electron Box,” IEEE Trans Nanotechnol, vol. 2, no. 1, pp. 15~22, Mar. 2003. [33] T. Fischer, M. Kewenig, D. A. Bozhko, A. A. Serga, I. I. Syvorotka, F. Ciubotaru, C. Adelmann, B. Hillebrands, and A. V. Chumak, “Experimental Prototype of a Spin-Wave Majority Gate,” Appl. Phys. Lett., vol. 110, no. 15, pp. 152401, Apr. 2017. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/80240 | - |
| dc.description.abstract | 本篇論文主要探討兩個相鄰的同心金氧半穿隧二極體之電荷耦合效應及其反應出的開路感測電壓現象，並利用開路感測電壓低功耗的優勢建立出在記憶體及邏輯計算元件上的應用。在本論文的第二章，我們透過對此兩相鄰之金氧半穿隧二極體做電流-電壓量測得出內部圓形元件會因為與來自外部圓環的少數載子流發生耦合現象而有飽和電流增加的效應。除此之外，進一步比較厚度對此現象的影響後，我們得出具有較薄氧化層之元件在耦合表現上有增益的效果。建立在此利用薄氧化層所造成的耦合機制，我們在本論文的第三章中提出利用此兩金氧半結構之開路電壓感測效應所達成的記憶體應用。此記憶體之窗口受到氧化層厚度、寫入時間以及不同運作模式所影響。為了印證在上述兩個章節中的實驗數據及其機制，我們也利用 SILVACO TCAD 軟體針對金氧半穿隧二極體之邊際電場及兩穿隧二極體之間的開路電壓感測進行模擬，發現此兩物理現象與厚度及氧化物陷阱電荷之間的趨勢均與實驗結果和我們所提出的機制相吻合。最後，我們透過將外圍環型金氧半結構切割成數個分離的元件之方式，將整個元件發展成一個多階開路電壓感測器，並進一步提出一個將其設計成能夠承載多輸入端且具低功耗特性之邏輯元件的想法，此有望解決傳統 CMOS 邏輯元件所遇到的困難。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-24T03:03:06Z (GMT). No. of bitstreams: 1 U0001-0707202122245300.pdf: 7563061 bytes, checksum: c726ff2ea2c840ecac646d7120b2fbae (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | "摘要…………………………………………………………………………………………………....................................I Abstract………………………………………………………………………………….....................................II Contents…………………………………………………………….………………......................................IV Table Caption.……………………………………………………………………....................................VI Figure Captions………………………………………………………………....................................VII Chapter 1 Introduction……………………………………………………………................................1 1-1 Motivation and Thesis Organization………………………………………….......................2 1-2 I-V Characteristics of MIS(p) Tunnel Diodes………………………………….................4 1-2-1 Effect of Oxide Thickness on I-V Characteristics……………………...............5 1-2-2 Effect of Additional Minority Carrier Supply………………………..................6 1-2-3 Current Dependencies on Area and Perimeter………………………....................7 1-2-4 Two States Phenomenon of Saturation Current of MIS(p) Tunnel Diodes.......................................................................8 1-3 TCAD Simulation……………………………………………………………..................................10 1-4 Growth Mechanism of Constant Voltage Anodization of Silicon.............11 1-5 Electrical Determination of Dielectric Thickness…………………………….............13 1-6 Summary…………………………………………………………………….......................................14 Chapter 2 Oxide Thickness Dependent Coupling Phenomenon between Two Concentric MIS TDs.........................................................................21 2-1 Introduction…………………………………………………………………...................................22 2-2 Experimental and TCAD Simulation……………………………………….........................23 2-3 Current-Voltage Characteristics of MIS(p) Tunnel Diodes………………..........…24 2-3-1 Current-Voltage Characteristics of Ring and Center MIS(p) Tunnel Diodes………………………………………………………………………...........................................24 2-3-2 Current-Voltage Characteristics of Center and Single center MIS(p) Tunnel Diodes……………………………………………………………...............................................26 2-4 Physical Mechanism of Saturation Current Coupling Effect……….............27 2-5 Capacitance-Voltage Characteristics of Single Center and Center MIS(p) Tunnel Diodes……………………………………………………………………............................................30 2-6 TCAD Simulation Result of Fringing Field Extension……………………….............31 2-7 Coupling Behavior of Ring MIS(p) TD……………………………………......................…32 2-8 Summary…………………………………………………………………….......................................35 Chapter 3 Memory Application of Coupled Open-Circuit Voltage Sensing…………....52 3-1 Introduction……..........................................................54 3-2 Experimental and TCAD Simulation….......................................54 3-3 The Relation between Current Coupling Behavior and Open- Circuit Voltage Sensitivity…................................................................55 3-3-1 Open-Circuit Voltage Sensing with Different Oxide Thickness….…........55 3-3-2 Current Coupling Behavior Influenced by Electron Trapping……..........…56 3-4 Memory Application Based on Open-Circuit Voltage Sensing …..............58 3-4-1 Memory Behavior with Different Biased Voltage…….......................58 3-4-2 Physical Mechanism of Memory Based on Open-Circuit Voltage Sensing....59 3-4-3 Memory Behavior with Different Stress Time…...........................60 3-4-4 Memory Window with Various Oxide Thickness............................61 3-4-5 Memory Behavior with Different Operation Configuration................61 3-5 Capacitance-Voltage Characteristics with Trapped Electrons ………..........63 3-6 TCAD Simulation Result …................................................64 3-7 Summary……...............................................................67 Chapter 4 Multi-Level Sensor Based on Coupled MIS TDs…………...................81 4-1 Introduction……..........................................................82 4-2 Experimental............................................................83 4-3 Multi-Level State of Output Voltage…....................................83 4-3-1 The Relation between Vin and Vout……...................................83 4-3-2 A Fitting Equation of Vout(Vin, n)……............................….....84 4-4 Operation as Logic Gates…...............................................86 4-5 Summary…................................................................87 Chapter 5 Conclusion and Future work………………….................................96 5-1 Conclusion……............................................................97 5-2 Suggestion for Future Work……............................................98 5-2-1 The Current-Voltage Characteristics of Ring MIS TD with Various Width…98 5-2-2 A Possible Refinement of Memory Application Based on Coupled MID TDs……99 5-2-3 An Extension of Multi-Level Sensor…..................................100 Reference….................................................................105" | |
| dc.language.iso | en | |
| dc.subject | 邏輯元件 | zh_TW |
| dc.subject | 記憶體 | zh_TW |
| dc.subject | 金氧半穿隧二極體 | zh_TW |
| dc.subject | 電荷耦合 | zh_TW |
| dc.subject | 開路電壓 | zh_TW |
| dc.subject | 少數載子流 | zh_TW |
| dc.subject | 邊際電場 | zh_TW |
| dc.subject | Coupling phenomenon | en |
| dc.subject | Logic device | en |
| dc.subject | Memory | en |
| dc.subject | Fringing field | en |
| dc.subject | Minority carriers supply | en |
| dc.subject | MIS tunneling diode | en |
| dc.subject | Open-circuit voltage | en |
| dc.title | 鄰近同心金屬-絕緣層-半導體穿隧二極體耦合效應及開路電壓感測之應用 | zh_TW |
| dc.title | Coupling Phenomenon between Adjacent Concentric Metal-Insulator-Semiconductor Tunnel Diodes and Its Application of Coupled Open-Circuit Voltage Sensing | en |
| dc.date.schoolyear | 109-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林致廷(Hsin-Tsai Liu),胡璧合(Chih-Yang Tseng) | |
| dc.subject.keyword | 金氧半穿隧二極體,電荷耦合,開路電壓,少數載子流,邊際電場,記憶體,邏輯元件, | zh_TW |
| dc.subject.keyword | MIS tunneling diode,Coupling phenomenon,Open-circuit voltage,Minority carriers supply,Fringing field,Memory,Logic device, | en |
| dc.relation.page | 110 | |
| dc.identifier.doi | 10.6342/NTU202101334 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2021-07-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| U0001-0707202122245300.pdf Access limited in NTU ip range | 7.39 MB | Adobe PDF |
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