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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
| dc.contributor.author | Jian-Yu Lin | en |
| dc.contributor.author | 林建宇 | zh_TW |
| dc.date.accessioned | 2022-11-23T09:29:49Z | - |
| dc.date.available | 2021-08-04 | |
| dc.date.available | 2022-11-23T09:29:49Z | - |
| dc.date.copyright | 2021-08-04 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-07-13 | |
| dc.identifier.citation | [1] R. H. Dennard, 'Field-effect transistor memory,' United States Patent Appl. 3387286, 1968. [2] S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, 'A capacitor-less 1T-DRAM cell,' IEEE Electron Device Letters, vol. 23, no. 2, pp. 85-87, 2002, doi: 10.1109/55.981314. [3] C. Kuo, K. Tsu-Jae, and H. Chenming, 'A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications,' IEEE Transactions on Electron Devices, vol. 50, no. 12, pp. 2408-2416, 2003, doi: 10.1109/TED.2003.819257. [4] S. Navarro et al., 'Reliability Study of Thin-Oxide Zero-Ionization, Zero-Swing FET 1T-DRAM Memory Cell,' IEEE Electron Device Letters, vol. 40, no. 7, pp. 1084-1087, 2019, doi: 10.1109/LED.2019.2915118. [5] Y. J. Yoon, J. H. Seo, S. Cho, J.-H. Lee, and I. M. Kang, 'A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance,' Applied Physics Letters, vol. 114, no. 18, p. 183503, 2019/05/06 2019, doi: 10.1063/1.5090934. [6] J. H. Seo et al., 'Fabrication and Characterization of a Thin-Body Poly-Si 1T DRAM With Charge-Trap Effect,' IEEE Electron Device Letters, vol. 40, no. 4, pp. 566-569, 2019, doi: 10.1109/LED.2019.2901003. [7] M. A. Green, F. D. King, and J. Shewchun, 'Minority carrier MIS tunnel diodes and their application to electron- and photo-voltaic energy conversion—I. Theory,' Solid-State Electronics, vol. 17, no. 6, pp. 551-561, 1974/06/01/ 1974, doi: https://doi.org/10.1016/0038-1101(74)90172-5. [8] J. Shewchun, M. A. Green, and F. D. King, 'Minority carrier MIS tunnel diodes and their application to electron- and photo-voltaic energy conversion—II. Experiment,' Solid-State Electronics, vol. 17, no. 6, pp. 563-572, 1974/06/01/ 1974, doi: https://doi.org/10.1016/0038-1101(74)90173-7. [9] M. Y. Doghish and F. D. Ho, 'A comprehensive analytical model for metal-insulator-semiconductor (MIS) devices,' IEEE Transactions on Electron Devices, vol. 39, no. 12, pp. 2771-2780, 1992, doi: 10.1109/16.168723. [10] C. Liao and J. Hwu, 'Remote Gate-Controlled Negative Transconductance in Gated MIS Tunnel Diode,' IEEE Transactions on Electron Devices, vol. 63, no. 7, pp. 2864-2870, 2016, doi: 10.1109/TED.2016.2565688. [11] M. Y. Doghish and F. D. Ho, 'A comprehensive analytical model for metal-insulator-semiconductor (MIS) devices: a solar cell application,' IEEE Transactions on Electron Devices, vol. 40, no. 8, pp. 1446-1454, 1993, doi: 10.1109/16.223704. [12] C. W. Liu, W. T. Liu, M. H. Lee, W. S. Kuo, and B. C. Hsu, 'A novel photodetector using MOS tunneling structures,' IEEE Electron Device Letters, vol. 21, no. 6, pp. 307-309, 2000, doi: 10.1109/55.843159. [13] S. Yen-Hao and H. Jenn-Gwo, 'An on-chip temperature sensor by utilizing a MOS tunneling diode,' IEEE Electron Device Letters, vol. 22, no. 6, pp. 299-301, 2001, doi: 10.1109/55.924848. [14] K. Tseng, C. Liao, and J. Hwu, 'Enhancement of Transient Two-States Characteristics in Metal-Insulator-Semiconductor Structure by Thinning Metal Thickness,' IEEE Transactions on Nanotechnology, vol. 16, no. 6, pp. 1011-1015, 2017, doi: 10.1109/TNANO.2017.2740943. [15] Y.-C. Yang, K.-W. Lin, and J.-G. Hwu, 'Transient Two-State Characteristics in MIS(p) Tunnel Diode with Edge-Thickened Oxide (ETO) Structure,' ECS Journal of Solid State Science and Technology, vol. 9, no. 10, p. 103006, 2020/11/03 2020, doi: 10.1149/2162-8777/abc576. [16] S. M. Sze and K. K. Ng, 'Tunnel Devices,' in Physics of Semiconductor Devices, 2006, pp. 415-465. [17] K. J. Yang and H. Chenming, 'MOS capacitance measurements for high-leakage thin dielectrics,' IEEE Transactions on Electron Devices, vol. 46, no. 7, pp. 1500-1501, 1999, doi: 10.1109/16.772500. [18] K. Yang, K. Ya-Chin, and H. Chenming, 'Quantum effect in oxide thickness determination from capacitance measurement,' in 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), 14-16 June 1999 1999, pp. 77-78, doi: 10.1109/VLSIT.1999.799348. [19] Berkeley Device Group QM CV Simulator [Online] Available: http://www-device.eecs.berkeley.edu/qmcv/qmcv.htm [20] C. Liao, W. Kao, and J. Hwu, 'Energy-Saving Write/Read Operation of Memory Cell by Using Separated Storage Device and Remote Reading With an MIS Tunnel Diode Sensor,' IEEE Journal of the Electron Devices Society, vol. 4, no. 6, pp. 424-429, 2016, doi: 10.1109/JEDS.2016.2591956. [21] C.-H. Chang and J.-G. Hwu, 'Trapping characteristics of Al2O3/HfO2/SiO2 stack structure prepared by low temperature in situ oxidation in dc sputtering,' Journal of Applied Physics, vol. 105, no. 9, p. 094103, 2009/05/01 2009, doi: 10.1063/1.3120942. [22] C. Lin and J. Hwu, 'Comparison of the Reliability of Thin Al2O3 Gate Dielectrics Prepared by In Situ Oxidation of Sputtered Aluminum in Oxygen Ambient With and Without Nitric Acid Compensation,' IEEE Transactions on Device and Materials Reliability, vol. 11, no. 2, pp. 227-235, 2011, doi: 10.1109/TDMR.2011.2108300. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/80168 | - |
| dc.description.abstract | 本論文旨在研究一種新型結構的金氧半穿隧二極體，其全名為具閘極邊界溝槽結構之金氧半穿隧二極體(以下簡稱為溝槽元件)。與傳統的平面型金氧半穿隧二極體相比(以下簡稱為平面元件)，此新型結構元件在電流–電壓、記憶體留存、記憶體耐久特性中不只展現了較低的反偏壓電流，更擁有較大的暫態電流，比如說在1000個週期的記憶體耐久量測中，溝槽結構元件的記憶體電流窗口比傳統結構元件大了25倍。從高頻率的電容–電壓量測中可以推測，溝槽元件中的少數載子數量(即電子)較平面元件少，這也被認為是造成其反偏壓電流較小的原因。此外，根據以上的推論，我們提出了一個模型來解釋為何溝槽元件的暫態電流行為比平面元件要來的更強。最後，不同等效氧化層厚度對暫態電流的影響也在本論文中被詳細探討，並且我們發現溝槽元件在很大的等效氧化層厚度範圍內，都具有比平面元件更好的記憶體電流窗口。由於較強的暫態電流特性與其所致的較佳記憶體電流窗口，具閘極邊界溝槽結構之金氧半穿隧二極體擁有作為揮發性記憶體的潛力。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-23T09:29:49Z (GMT). No. of bitstreams: 1 U0001-2606202123002100.pdf: 18087942 bytes, checksum: 8bfcdbc3167adf2740d534f0796c3506 (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | 誌謝 ......................................................... I 摘要 ........................ III Abstract ................ IV Contents ........................ V Figure Captions ............................................... VII Chapter 1 Introduction ............................................ 1 1-1. Motivation ....................... 2 1-2. Fundamentals of MIS(p) TD ............................................. 4 1-2-1. Deep Depletion Phenomenon in C–V Curves ............................... 4 1-2-2. Thickness Dependency of Reverse Bias Current ......................... 6 1-2-3. Perimeter Dependency of Reverse Bias Current ......................... 7 1-3. Equivalent Oxide Thickness (EOT) Extraction ............................ 9 1-4. Summary ............................................................. 11 Chapter 2 I–V and C–V Characteristics of Trench MIS TDs ................... 16 2-1. Introduction ....................................................... 17 2-2. Experimental ..................................................... 17 2-3. Results and Discussion .............................................. 19 2-3-1. Lower Reverse Bias Current of Trench MIS TDs ........................... 20 2-3-2. Similar Forward Bias Capacitance and Current of MIS TDs ............... 24 2-4. Summary .......................................................... 25 Chapter 3 Transient Current Behavior of Trench MIS TDs .................... 32 3-1. Introduction .................................................... 33 3-2. Results and Discussion .................................................... 33 3-2-1. I–V Characteristics with Different Sweeping Rates ....................... 33 3-2-2. Memory Retention and Endurance Properties ............................. 35 3-2-3. Thermal Equilibrium Model of Transient Current ........................... 37 3-2-4. Verification of Thermal Equilibrium Model .............................. 41 3-2-4-1. Experimental Results .............................................. 41 3-2-4-2. Transient TCAD Simulation ........................................... 43 3-3. Summary ............................................................. 45 Chapter 4 Influence of EOT on Transient Current Behavior of MIS TDs .......... 60 4-1. Introduction ........................................................ 61 4-2. Results and Discussion ................................................. 61 4-2-1. I–V Curves with Different EOTs ........................................ 61 4-2-2. Memory Retention Properties with Different EOTs ..................... 62 4-2-3. Transient TCAD Simulation of MIS TDs with Different EOTs ................. 64 4-3. Summary ................................................................ 66 Chapter 5 Conclusion and Future Work ....................................... 75 5-1. Conclusion ................................................................. 76 5-2. Future Work .............................................................. 78 5-2-1. The Distance Between the Gate Edge and the Trench Edge ................ 78 5-2-2. The Depth of the Trench ............................................. 79 5-2-3. Effect of Different Sidewall Materials on the Transient Current Behavior ..79 References.......................................................... 87 | |
| dc.language.iso | en | |
| dc.subject | 金氧半穿隧二極體 | zh_TW |
| dc.subject | 記憶體特性 | zh_TW |
| dc.subject | 溝槽結構 | zh_TW |
| dc.subject | 暫態電流行為 | zh_TW |
| dc.subject | memory property | en |
| dc.subject | trench structure | en |
| dc.subject | metal-insulator-semiconductor (MIS) tunnel diode (TD) | en |
| dc.subject | transient current behavior | en |
| dc.title | 具閘極邊界溝槽結構之金氧半穿隧二極體之暫態電流強化行為 | zh_TW |
| dc.title | Enhanced Transient Current Behavior in MIS(p) Tunnel Diode with Gate Edge Trench Structure | en |
| dc.date.schoolyear | 109-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.author-orcid | 0000-0002-8800-8714 | |
| dc.contributor.advisor-orcid | 胡振國(0000-0001-9688-0812) | |
| dc.contributor.oralexamcommittee | 胡璧合(Hsin-Tsai Liu),林致廷(Chih-Yang Tseng) | |
| dc.subject.keyword | 金氧半穿隧二極體,暫態電流行為,溝槽結構,記憶體特性, | zh_TW |
| dc.subject.keyword | metal-insulator-semiconductor (MIS) tunnel diode (TD),transient current behavior,trench structure,memory property, | en |
| dc.relation.page | 89 | |
| dc.identifier.doi | 10.6342/NTU202101152 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2021-07-14 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| U0001-2606202123002100.pdf | 17.66 MB | Adobe PDF | 檢視/開啟 |
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