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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/79574完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
| dc.contributor.author | Ming-Han Tsai | en |
| dc.contributor.author | 蔡明翰 | zh_TW |
| dc.date.accessioned | 2022-11-23T09:04:06Z | - |
| dc.date.available | 2021-11-08 | |
| dc.date.available | 2022-11-23T09:04:06Z | - |
| dc.date.copyright | 2021-11-08 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-09-17 | |
| dc.identifier.citation | NIST,“Post-quantumcryptographystandardization,”2020,https://csrc.nist.gov/Projects/Post-Quantum-Cryptography/Post-Quantum-Cryptography-Standardization. D. J. Bernstein, C. Chuengsatiansup, T. Lange, and C. van Vredendaal, “NTRU Prime: round 3,” Post-Quantum Cryptography Standardization Project, NIST, 2020, https://ntruprime.cr.yp.to/nist/ntruprime-20201007.pdf. A. Marotzke, “A Constant Time Full Hardware Implementation of Streamlined NTRU Prime,” Cryptology ePrint Archive, Report 2020/1067, 2020, https://eprint.iacr.org/2020/1067. J. Hoffstein, J. Pipher, and J. H. Silverman, “NTRU: A ring-based public key cryptosystem,” in Algorithmic Number Theory, J. P. Buhler, Ed. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998, pp. 267–288. P. Shor, “Algorithms for quantum computation: discrete logarithms and factoring,” in Proceedings 35th Annual Symposium on Foundations of Computer Science, 1994, pp.124–134. D. J. Bernstein, C. Chuengsatiansup, T. Lange, and C. van Vredendaal, “NTRU Prime: reducing attack surface at low cost,” Cryptology ePrint Archive, Report 2016/461,2016, https://eprint.iacr.org/2016/461. N. Howgrave-Graham, “A hybrid lattice-reduction and meet-in-the-middle attack against NTRU,” in Advances in Cryptology - CRYPTO 2007, A. Menezes, Ed. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007, pp. 150–169. D. J. Bernstein and B.-Y. Yang, “Fast constant-time gcd computation and modular inversion,” IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2019, no. 3, pp. 340–398, May 2019. [Online]. Available: https://tches.iacr.org/index.php/TCHES/article/view/8298 E. Alkim, D. Y.-L. Cheng, C.-M. M. Chung, H. Evkan, L. W.-L. Huang, V. Hwang, C.-L. T. Li, R. Niederhagen, C.-J. Shih, J. W¨alde, and B.-Y. Yang, “Polynomial Multiplication in NTRU Prime: Comparison of Optimization Strategies on Cortex-M4,” Cryptology ePrint Archive, Report 2020/1216, 2020, https://eprint.iacr.org/2020/1216. I. J. Good, “Random motion on a finite abelian group,” Proceedings of the Cambridge Philosophical Society, vol. 47, no. 3, pp. 756–762, May 1951. N. Zhang, B. Yang, C. Chen, S. Yin, S.Wei, and L. Liu, “Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT,” IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2020, no. 2, pp. 49–72, Mar.2020. [Online]. Available: https://tches.iacr.org/index.php/TCHES/article/view/8544 H.-F. Lo, M.-D. Shieh, and C.-M. Wu, “Design of an efficient FFT processor for DAB system,” in ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), vol. 4, 2001, pp. 654–657 vol. 4. W.-C. Pai, “Fast constant-time modular inversion on FPGA,” Master’s thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2019, https://hdl.handle.net/11296/fem7j9. H.-C. Liu, “An FPGA implementation of the NTRU Prime Cryptosystem,” Master’s thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2020, https://hdl.handle.net/11296/g2wzwh. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/79574 | - |
| dc.description.abstract | 隨著量子電腦的出現，現有的公鑰密碼演算法已不安全，因此美國國家標準暨技術研究院(NIST)開始徵集能抵抗量子電腦攻擊的後量子密碼演算法，其徵集的演算法分為公鑰加密(密鑰交換)和數位簽章，在第三輪的NIST後量子密碼學標準化進程中，NTRU Prime是其中一種公鑰加密的備選者。本篇論文在被NIST所接受的Xilinx Artix-7 FPGA上實作Streamlined NTRU Prime密碼系統。我們實現了一個脈動架構的多項式模反元素計算和Good’s trick 數論轉換多項式乘法，它們分別是密鑰生成和封裝/解封裝的核心功能。對於NIST安全級別3，密鑰生成的實作使用915個slices、10.5個BRAMs和8個DSPs；封裝/解封裝的實作使用 3270個slices，16.5個BRAMs和7個DSPs。密鑰生成的最高實現頻率為111MHz，而封裝/解封裝為77MHz，受雜湊函數所限。密鑰生成、封裝和解封裝分別需要8404μs、645μs和1523μs。據我們所知，這是首個在Xilinx Artix-7 FPGA上的硬體實作。為了與Streamlined NTRU Prime的其他最新實作進行比較，我們也在Xilinx Zynq Ultrascale+ FPGA上實作其核心功能。在幾乎相同的執行時間下，多項式模反元素計算的slice數量減少47%，而多項式乘法的slice數量減少20%且執行時間減少62%。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-23T09:04:06Z (GMT). No. of bitstreams: 1 U0001-1609202116285300.pdf: 2363006 bytes, checksum: 91932f3f9e54041d15fd718f8b43472b (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | 口試委員會審定書 i 致謝 ii 中文摘要 iii Abstract iv List of Figures vii List of tables viii 1 Introduction 1 2 Background 3 2.1 NTRU 3 2.2 NTRU Prime 5 2.3 Related Work 8 3 Implementation 10 3.1 Constant-time Polynomial Inversion 11 3.1.1 Architecture of Polynomial Inversion 13 3.1.2 Memory Access Scheme 14 3.1.3 Ideal Cycle Count 15 3.1.4 Systolic Architecture of Polynomial Inversion 16 3.2 Polynomial Multiplication 18 3.2.1 Good’s Trick NTT Multiplication 18 3.2.2 Architecture of Good’s Trick NTT Multiplication 20 3.2.3 Memory Access Scheme 20 3.2.4 Butterfly Unit 23 3.2.5 Chinese Reminder Theorem 24 3.2.6 Ideal Cycle Count 26 4 Result 27 4.1 Implementation Result 27 4.2 Comparison With Other Implementations 29 5 Conclusion and future work 32 Reference 33 | |
| dc.language.iso | en | |
| dc.title | 在現場可程式化邏輯閘陣列上實作有效率的流線型吾乃數論家別版 | zh_TW |
| dc.title | An efficient FPGA implementation of Streamlined NTRU Prime | en |
| dc.date.schoolyear | 109-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 楊柏因(Hsin-Tsai Liu),鄭振牟(Chih-Yang Tseng),蕭旭君 | |
| dc.subject.keyword | 美國國家標準暨技術研究院,後量子密碼學,NTRU Prime,Streamlined NTRU Prime,FPGA實作,多項式模反元素,多項式乘法, | zh_TW |
| dc.subject.keyword | NIST,post-quantum cryptography,NTRU Prime,Streamlined NTRU Prime,FPGA implementation,polynomial inversion,polynomial multiplication, | en |
| dc.relation.page | 34 | |
| dc.identifier.doi | 10.6342/NTU202103214 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2021-09-22 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| U0001-1609202116285300.pdf | 2.31 MB | Adobe PDF | 檢視/開啟 |
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