次微米線寬P-型錫鎳氧化物薄膜電晶體之研究

Abstract

本研究以射頻磁控濺鍍系統共濺鍍沉積p型SnNiOx主動層，並分別以黃光顯影以及電子束顯影定義微米線寬通道以及次微米線寬通道，成功製備p型SnNiOx次微米線寬薄膜電晶體。研究主題主要分成三項：次微米線寬效應 (窄線寬效應)、主動層退火溫度最佳化以及閘極偏壓穩定性測試。 次微米線寬效應部分調整通道長寬比由0.4微米/20微米到40微米/20微米。當線寬縮小時，薄膜電晶體能展現更高的載子遷移率。此現象可能是因為當以含氟電漿進行蝕刻製程時，會產生金屬-氟鍵結、減少介面能態，因此，當線寬縮小時，通道邊緣比例相對較大，受到氟電漿效應影響更明顯，從而得到更高的載子遷移率。 另一方面，本研究也對主動層退火溫度的製程進行最佳化，退火溫度調整範圍由185℃到245℃。當退火溫度為185℃，薄膜電晶體有很高的通道電流但無法操作，推測原因為主動層的不完全氧化和過量的金屬含量。當退火溫度為205℃元件開始具有場效特性，而當到達225℃時，可以有高達14 cm2V-1s-1的載子遷移率，推測是因為退火225℃後能使晶相及金屬成分含量達到最適值。而當退火溫度上升到245℃，由於主動層過度氧化，載子遷移率出現衰退的現象。 最後對前退溫度225℃、長寬比0.4微米/20微米和40微米/20微米的薄膜電晶體閘極偏壓穩定性測試。對微米線寬通道薄膜電晶體，施加負閘極偏壓後，有-0.6 V的臨界電壓偏移，意味負閘極偏壓引起的電洞侷阱效應是較小的；施加正閘極偏壓後，有高達1.4 V的臨界電壓偏移，推測是因為主動層和主動層/絕緣層介面的載子侷阱效應。另一方面，對次微米線寬通道薄膜電晶體，施加負、正閘極偏壓後，分別有-1.2 V、2.0 V的臨界電壓偏移。相對於微米線寬通道薄膜電晶體有稍微大的臨界電壓偏移，推測是因為次微米線寬通道薄膜電晶體沒有受到鈍化層保護的通道邊緣比例較大，因此較容易受到環境水氧影響，造成較大臨界電壓偏移。

In this research, p-type SnNiOx Thin-film transistors (TFTs) with submicron-channel widths have been fabricated. The active layer SnNiOx was deposited by rf magnetron sputtering and defined by e-beam lithography. The characterization of SnNiOx TFTs were divided into three sections：Effects of submicron channel width (narrow channel effect), Optimization of active layer annealing temperature, and Gate bias stability test for the optimal samples. In order to study the effects of submicron channel width, the channel geometry of SnNiOx active layer was defined to be W/L = 0.4 μm/20 μm, 0.6 μm/20 μm, 1.0 μm/20 μm, 3.0 μm/20 μm, 40 μm/20 μm. An enhancement in mobility could be obtained as channel width decreases, which might be due to the larger specific fringe surface area of the narrow channel. Due to the ability of the metal-F bond formation by F plasma during CF4 etching to decrease the interface state density, the narrow channel width TFTs with larger specific fringe surface area had better mobility. On the other hand, the optimization of annealing temperature was also investigated. The annealing temperature of the SnNiOx active layer was tuned from 185℃ to 245℃. For an annealing temperature of 185℃, the TFTs showed quite a high source-to-drain current but no modulation, which might be caused by insufficient oxidation of the active layer and the presence of excess metal content. For the annealing temperature of 205℃, the TFT started to be able to modulate. When the annealing temperature reached 225℃, the TFT reached the best mobility of 14 cm2V-1s-1, which might represent the best crystal phase as well as the appropriate residual metal amount. If the temperature went as high as 245℃, the mobility would degrade, which might be due to the over oxidation of the active layer Finally, the gate-bias stress stability of TFTs with channel dimensions of W/L = 40 μm/20 μm and W/L = 0.4 μm/20 μm were studied and compared. For the micron channel width TFTs, the ΔVth for negative gate bias stress was as small as -0.6 V, which implied that the negative gate bias stress induced hole trapping was negligible; on the other hand, the large ΔVth of 1.4 V for positive gate bias stress might be caused by the charge trapping in the SnNiOx/HfO2 interface and SnNiOx channel layer. For submicron channel width TFTs, the ΔVth for negative and positive gate bias stress were -1.2 and 2.0 V, respectively. The slightly larger ΔVth might be due to the fringe of the channel that was not covered by the SiNx passivation layer, and the proportion of fringe of the submicron channel TFTs that were larger than that of the micron channel TFTs; therefore, becoming easier targets for oxygen and moisture in the environment.