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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳奕君 | |
dc.contributor.author | Chun-Chen Wang | en |
dc.contributor.author | 王淳真 | zh_TW |
dc.date.accessioned | 2021-07-11T15:31:50Z | - |
dc.date.available | 2023-08-23 | |
dc.date.copyright | 2018-08-23 | |
dc.date.issued | 2018 | |
dc.date.submitted | 2018-08-16 | |
dc.identifier.citation | [1] L. J. Edgar, 'Method and apparatus for controlling electric currents,' 1930.
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78952 | - |
dc.description.abstract | 本研究成功地於5.5 µm透明聚醯亞胺(polyimide, PI)基板上開發全透明可撓性非晶氧化銦鎵鋅薄膜電晶體,並利用透明聚醯亞胺封裝層使元件位處於中性面上,進而有效降低機械應變對元件特性的影響。研究中先針對非全透明可撓性非晶氧化銦鎵鋅薄膜電晶體進行優化,包括主動層厚度、退火程序及封裝層效果的探討。接著,將金屬電極置換為氧化銦錫透明電極,製作全透明可撓性非晶氧化銦鎵鋅薄膜電晶體,並研究其在不同彎曲程度下的電性及偏壓應力穩定性。
在基板的準備上,以矽晶圓為承載基板,在旋轉塗佈聚醯亞胺前驅物後,以400℃進行固化,接著利用電漿輔助化學氣相沉積系統於350℃沉積二氧化矽及氮化矽緩衝層,此5.8 µm複合基板(聚醯亞胺與緩衝層)之等效楊氏模數約為2.55 GPa。在電晶體的製作上,先針對無背通道鈍化層之元件進行優化,以氧化銦鎵鋅為靶材,利用射頻磁控濺鍍系統於室溫下分別沉積15、30、50 nm薄膜電晶體通道層,緊接著於空氣中以350℃退火,再完成元件後續製程,結果發現通道層為15 nm的元件具較佳的電性表現。接著對此元件進行背通道鈍化,但在沉積二氧化矽鈍化層時,因電漿轟擊導致通道層及介電層因遭受破壞,故將製程調整為先沉積鈍化層再退火,以妥善修復通道層之缺陷。接著以330℃固化的5.5 µm聚醯亞胺作為封裝層,最後以機械方式離型,完成全透明可撓性非晶氧化銦鎵鋅薄膜電晶體的製作。 所獲得之薄膜電晶體的臨界電壓為1.94 V、次臨界擺幅為0.342 V/dec、飽和載子遷移率為13.36 cm^2/Vs、電流開關比為17.45×10^8。當其於曲率半徑為±5 cm至±0.5 cm的張應變及壓應變下,電性特徵參數變化皆不明顯,表示聚醯亞胺封裝層具有不錯的應力平衡效果。於偏壓穩定性測試時,具封裝的全透明可撓性非晶氧化銦鎵鋅薄膜電晶體展現了較小的臨界電壓偏移量,此乃由於二氧化矽鈍化層有效隔絕空氣中的水氧,而聚醯亞胺封裝層有效降低穿透光源能量,使全透明可撓性非晶氧化銦鎵鋅薄膜電晶體獲得良好的偏壓穩定性。 | zh_TW |
dc.description.abstract | In this study, a fully transparent flexible amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistor (TFT) was successfully developed on a 5.5 µm transparent polyimide (PI) substrate. A transparent PI encapsulation layer was adopted to ensure that the device was located on a neutral plane, thereby effectively lowering the effects of mechanical strain on device characteristics. First, the flexible a-IGZO thin-film transistor was optimized in the following aspects: the thickness of the active layer, the annealing procedures, and the effectiveness of the encapsulation layer. Subsequently, metal electrodes were replaced by transparent indium tin oxide (ITO) electrodes to produce a fully transparent flexible a-IGZO thin-film transistor. The electrical characteristics and the stability of bias stress at various degrees of bending were also investigated.
For PI substrate preparation, a silicon wafer served as a carrier substrate. The precursor of PI was spin-coated on the substrate and then curing at 400°C. A plasma-enhanced chemical vapor deposition system was subsequently adopted to deposit silicon dioxide and silicon nitride buffer layers. The equivalent Young’s modulus of this 5.8 µm composite substrate (i.e., constructed using PI and buffer layers) was approximately 2.55 GPa. Regarding transistor production, devices without passivation layers were optimized first. IGZO was adopted as the target material. RF sputtering method was utilized to deposit it to form channel layers that were 15, 30, and 50 nm thick for the thin-film transistor at room temperature. Next, the materials underwent annealing in air at 350℃ to proceed to the subsequent processes. The results revealed that the devices with a 15 nm channel layer exhibited optimal electrical characteristics. This device was later subject to back channel passivation. However, during the deposition of the silicon dioxide passivation layer, the channel layer and dielectric layer were damaged due to plasma bombardment. Therefore, the process was adjusted to first performing passivation layer deposition and then annealing to properly repair the defects in the channel layer. Subsequently, the 5.5 µm PI cured at 330℃ was used as the encapsulation layer, and mechanical debonding was applied to complete the production of the fully transparent and flexible a-IGZO thin-film transistor. For the obtained thin-film transistor, the threshold voltage was 1.94 V, the subthreshold swing was 0.342 V/dec, the saturation carrier mobility was 13.36 cm^2/Vs, and the current on/off ratio was 7.45 × 10^8. With a radius curvature of ±5 cm to ±0.5 cm, the thin-film transistor did not exhibit notable parameter changes in its electrical characteristics when tensile strain and compressive strain were applied to it, indicating that the PI encapsulation layer exhibited a satisfactory effect in maintaining stress equilibrium. In the bias stability test, the encapsulated, fully transparent flexible a-IGZO thin-film transistor exhibited a relatively small threshold voltage offset. This was because the silicon dioxide passivation layer effectively isolated the water and oxygen in the air, and the PI encapsulation layer effectively reduced the light source intensity. Accordingly, the fully transparent and flexible a-IGZO thin-film transistor acquired excellent bias stability. | en |
dc.description.provenance | Made available in DSpace on 2021-07-11T15:31:50Z (GMT). No. of bitstreams: 1 ntu-107-R05941112-1.pdf: 12585782 bytes, checksum: 2fd2e96fec70daa42b9c029309b86e57 (MD5) Previous issue date: 2018 | en |
dc.description.tableofcontents | 致謝 1
中文摘要 2 Abstract 4 目錄 7 圖目錄 10 表目錄 17 第一章 緒論 19 1.1 全透明可撓性薄膜電晶體發展背景與應用 19 1.2 研究動機 21 1.3 論文架構 22 第二章 理論與文獻回顧 24 2.1 薄膜電晶體簡介 24 2.1.1 薄膜電晶體之元件結構 24 2.1.2 薄膜電晶體之工作原理 25 2.1.3 薄膜電晶體之特徵參數 26 2.2 氧化銦鎵鋅半導體簡介 30 2.2.1 氧化銦鎵鋅之發展 30 2.2.2 氧化銦鎵鋅之材料特性 32 2.3 可撓性軟性聚醯亞胺基板簡介 34 2.4 全透明可撓性氧化銦鎵鋅薄膜電晶體文獻回顧 37 第三章 實驗方法與步驟 51 3.1 聚醯亞胺固化製程 51 3.2 薄膜沉積方法 52 3.2.1 電漿輔助化學氣相沉積系統 52 3.2.2 電子束蒸鍍系統 53 3.2.3 原子層沉積系統 54 3.2.4 射頻磁控式濺鍍系統 55 3.3 微影製程 56 3.4 蝕刻製程 59 3.4.1 濕式蝕刻製程 59 3.4.2 乾式蝕刻製程 59 3.5 可撓性透明氧化銦鎵鋅薄膜電晶體製程 61 3.6 量測分析方法 68 3.6.1 奈米壓痕試驗 68 3.6.2 X光繞射儀 72 3.6.3 紫外光/可見光光譜儀 73 3.6.4 薄膜電晶體特性量測方法 75 3.6.5 薄膜電晶體偏壓穩定性測試方法 75 3.6.6 彎曲測試量測方法 76 第四章 實驗結果與討論 81 4.1 聚醯亞胺薄膜分析 81 4.1.1 聚醯亞胺膜厚分析 81 4.1.2 聚醯亞胺薄膜楊氏模數與硬度分析 82 4.2 氧化銦鎵鋅薄膜分析 84 4.2.1 氧化銦鎵鋅結晶相分析 84 4.2.2 氧化銦鎵鋅之光學能隙分析 85 4.3 可撓性氧化銦鎵鋅薄膜電晶體元件特性分析 86 4.3.1 主動層厚度對可撓性氧化銦鎵鋅薄膜電晶體電性之影響 86 4.3.2 後退火程序對背通道鈍化層與可撓性氧化銦鎵鋅薄膜電晶體電性之影響 89 4.3.3 聚醯亞胺封裝層對可撓性氧化銦鎵鋅薄膜電晶體電性之影響 92 4.3.4 可撓性銦氧化銦鎵鋅薄膜電晶體彎曲下之元件特性分析 96 4.4 全透明可撓性氧化銦鎵鋅薄膜電晶體元件分析 100 4.4.1 全透明可撓性氧化銦鎵鋅薄膜電晶體之光學特性分析 100 4.4.2 全透明可撓性氧化銦鎵鋅薄膜電晶體之元件特性分析 102 4.4.3 全透明可撓性氧化銦鎵鋅薄膜電晶體彎曲下之元件特性分析 110 4.4.4 全透明可撓性氧化銦鎵鋅薄膜電晶體之偏壓穩定性分析 116 第五章 結論與未來展望 125 5.1 結論 125 5.2 未來展望 127 A. 附錄 128 I. 聚醯亞胺薄膜奈米壓痕測試原始數據 128 II. 全透明可撓性氧化銦鎵鋅薄膜電晶體於彎曲測試時各層薄膜之應變分析 130 參考文獻 132 | |
dc.language.iso | zh-TW | |
dc.title | 全透明可撓性氧化銦鎵鋅薄膜電晶體之研究 | zh_TW |
dc.title | Fully Transparent Flexible a-InGaZnO Thin-Film Transistors | en |
dc.type | Thesis | |
dc.date.schoolyear | 106-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳建彰,吳育任,徐振哲 | |
dc.subject.keyword | 可撓性電子元件,n型氧化物半導體,薄膜電晶體,非晶氧化銦鎵鋅,彎曲測試,偏壓穩定性, | zh_TW |
dc.subject.keyword | flexible electronics,n-type oxide semiconductor,thin-film transistor(TFT),indium–gallium–zinc–oxide (a-IGZO),bending test,gate-bias stress stability, | en |
dc.relation.page | 141 | |
dc.identifier.doi | 10.6342/NTU201803749 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2018-08-16 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
dc.date.embargo-lift | 2023-08-23 | - |
顯示於系所單位: | 電機工程學系 |
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