請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78922
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭大維 | |
dc.contributor.author | Shu-Hsien Liao | en |
dc.contributor.author | 廖書賢 | zh_TW |
dc.date.accessioned | 2021-07-11T15:29:24Z | - |
dc.date.available | 2021-08-18 | |
dc.date.copyright | 2018-08-18 | |
dc.date.issued | 2018 | |
dc.date.submitted | 2018-08-17 | |
dc.identifier.citation | [1] Yohwan Koh. Nand flash scaling beyond 20nm. May 2009.
[2] Yu Cai, Erich F Haratsch, Onur Mutlu, and Ken Mai. Error patterns in mlc nand flash memory: Measurement, characterization, and analysis. In Proceedings of the Conference on Design, Automation and Test in Europe, pages 521–526. EDA Consortium, 2012. [3] Ki-Tae Park, Myounggon Kang, Doogon Kim, Soon-Wook Hwang, Byung Yong Choi, Yeong-Taek Lee, Changhyun Kim, and Kinam Kim. A zeroing cell-to-cell interference page architecture with temporary lsb storing and parallel msb program scheme for mlc nand flash memories. IEEE Journal of Solid-State Circuits, 43(4): 919–928, 2008. [4] Yu Cai, Onur Mutlu, Erich F Haratsch, and Ken Mai. Program interference in mlc nand flash memory: Characterization, modeling, and mitigation. In Computer Design (ICCD), 2013 IEEE 31st International Conference on, pages 123–130. IEEE, 2013. [5] Alvin Cox. Solid state drive (ssd) requirements and endurance test method, 2011. [6] Kang-Deog Suh, Byung-Hoon Suh, Young-Ho Lim, Jin-Ki Kim, Young-Joon Choi, Yong-Nam Koh, Sung-Soo Lee, Suk-Chon Kwon, Byung-Soon Choi, Jin-Sun Yum, et al. A 3.3 v 32 mb nand flash memory with incremental step pulse programming scheme. IEEE Journal of Solid-State Circuits, 30(11):1149–1156, 1995. [7] Yu-Ming Chang, Yung-Chun Li, Ping-Hsien Lin, Hsiang-Pang Li, and Yuan-Hao Chang. Realizing erase-free slc flash memory with rewritable programming design. In Hardware/Software Codesign and System Synthesis (CODES+ ISSS), 2016 International Conference on, pages 1–10. IEEE, 2016. [8] Yong Sung Cho, Il Han Park, Sang Yong Yoon, Nam Hee Lee, Sang Hyun Joo, Ki-Whan Song, Kihwan Choi, Jin-Man Han, Kye Hyun Kyung, and Young-Hyun Jun. Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell nand flash. IEEE Journal of Solid-State Circuits, 48(4):948–959, 2013. [9] Guiqiang Dong, Yangyang Pan, and Tong Zhang. Using lifetime-aware progressive programming to improve slc nand flash memory write endurance. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(6):1270–1280, 2014. [10] Myungsuk Kim, Jaehoon Lee, Sungjin Lee, Jisung Park, and Jihong Kim. Improving performance and lifetime of large-page nand storages using erase-free subpage programming. In Design Automation Conference (DAC), 2017 54th ACM/EDAC/IEEE, pages 1–6. IEEE, 2017. [11] Seung-Hwan Shin, Dong-Kyo Shim, Jae-Yong Jeong, Oh-Suk Kwon, Sang-Yong Yoon, Myung-Hoon Choi, Tae-Young Kim, Hyun-Wook Park, Hyun-Jun Yoon, Young-Sun Song, et al. A new 3-bit programming algorithm using slc-to-tlc migration for 8mb/s high performance tlc nand flash memory. In VLSI Circuits (VLSIC), 2012 Symposium on, pages 132–133. IEEE, 2012. [12] Yixin Luo, Yu Cai, Saugata Ghose, Jongmoo Choi, and Onur Mutlu. Warm: Improving nand flash memory lifetime with write-hotness aware retention management. In Mass Storage Systems and Technologies (MSST), 2015 31st Symposium on, pages 1–14. IEEE, 2015. [13] Tseng-Yi Chen, Yuan-Hao Chang, Chien-Chung Ho, and Shuo-Han Chen. Enabling sub-blocks erase management to boost the performance of 3d nand flash memory. In Proceedings of the 53rd Annual Design Automation Conference, page 92. ACM, 2016. [14] Hsin-Yu Chang, Chien-Chung Ho, Yuan-Hao Chang, Yu-Ming Chang, and Tei-Wei Kuo. How to enable software isolation and boost system performance with sub-block erase over 3d flash memory. In Hardware/Software Codesign and System Synthesis (CODES+ ISSS), 2016 International Conference on, pages 1–10. IEEE, 2016. [15] Guiqiang Dong, Shu Li, and Tong Zhang. Using data postcompensation and predistortion to tolerate cell-to-cell interference in mlc nand flash memory. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(10):2718–2728, 2010. [16] Jae-Duk Lee, Sung-Hoi Hur, and Jung-Dal Choi. Effects of floating-gate interference on nand flash memory cell operation. IEEE Electron Device Letters, 23(5):264–266, 2002. [17] Ki-Tae Park, Sangwan Nam, Daehan Kim, Pansuk Kwak, Doosub Lee, Yoon-He Choi, Myung-Hoon Choi, Dong-Hun Kwak, Doo-Hyun Kim, Min-Su Kim, et al. Three-dimensional 128 gb mlc vertical nand flash memory with 24-wl stacked layers and 50 mb/s high-speed programming. IEEE Journal of Solid-State Circuits, 50(1): 204–213, 2015. [18] Avishay Traeger, Erez Zadok, Nikolai Joukov, and Charles P Wright. A nine year study of file system and storage benchmarking. ACM Transactions on Storage (TOS), 4(2):5, 2008. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78922 | - |
dc.description.abstract | 近年來,快閃記憶體的儲存密度逐漸上升。新興的高密度裝置,像是多級單元或三級單元的可靠度比較低,所以需要較強的錯誤更正碼以承受更多的寫入/抹除次數。然而較強的錯誤更正碼需要額外空間及效能的管理費用,且他需要昂貴的硬體支援。若裝置可以在固定的寫入/抹除次數中承受更多次的寫入的話,裝置的寫入/抹除次數以及錯誤更正碼成本的需求就可以被減緩。在此篇論文中,我們提出了一個考慮干擾的頁面重寫機制並使用他來儲存熱數據,使裝置在固定寫入/抹除次數下可以承受更多次的寫入。我們將會藉由一系列的實驗驗證此機制的能力。最後結果顯現出藉由我們提出的機制,我們可以讓裝置不犧牲耐久度的情況下減少寫入/抹除次數以及錯誤更正碼的需求成本。 | zh_TW |
dc.description.abstract | The density of NAND flash device continues to increase in recent years. Emerging high density devices like MLC or TLC has lower reliability and requires stronger ECC to tolerate more number of P/E cycle. However, strong ECC brings space and performance overhead, and it requires costly hardware support. If the device can tolerate more number of writes within fixed P/E cycle, the P/E cycle and ECC requirement can be relaxed. In this work, we propose a disturbance-aware page rewriting and use it to store write-hot data so that the number of write operations a device can tolerated within fixed P/E cycle can be improved. The capability of the proposed design is evaluated by a series of experiments, and the results show that with our proposed design, the P/E cycle as well as the ECC requirement can be reduced without sacrificing its endurance. | en |
dc.description.provenance | Made available in DSpace on 2021-07-11T15:29:24Z (GMT). No. of bitstreams: 1 ntu-107-R05922072-1.pdf: 1721919 bytes, checksum: 920b6affd874acfbf5db6421c7ad30c0 (MD5) Previous issue date: 2018 | en |
dc.description.tableofcontents | 口試委員會審訂書 i
中文摘要 ii Abstract iii Contents iv List of Figures v List of Tables vi 1 Introduction 1 2 Background And Motivation 4 3 Disturbance-Aware Page Rewriting Design 8 3.1 Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Disturbance-Aware Page Rewriting . . . . . . . . . . . . . . . . . . . . . 11 3.3 Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 Disturbance Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 Overhead Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Experiment Results 18 4.1 Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Experiment Results and Discussion . . . . . . . . . . . . . . . . . . . . . 19 5 Conclusions 23 Bibliography 24 | |
dc.language.iso | en | |
dc.title | 如何用頁面重寫降低快閃記憶體中錯誤更正碼的成本 | zh_TW |
dc.title | How to Reduce The ECC Cost of NAND Flash Memory
With Page Rewriting | en |
dc.type | Thesis | |
dc.date.schoolyear | 106-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 張原豪 | |
dc.contributor.oralexamcommittee | 修丕承,王克中,徐慰中 | |
dc.subject.keyword | 快閃記憶體,耐久度,重寫,錯誤更正碼,系統, | zh_TW |
dc.subject.keyword | NAND flash memory,Endurance,Rewriting,Error Correction Code,System, | en |
dc.relation.page | 26 | |
dc.identifier.doi | 10.6342/NTU201803807 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2018-08-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-107-R05922072-1.pdf 目前未授權公開取用 | 1.68 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。