請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78847
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
dc.contributor.author | Feng-Jen Chiang | en |
dc.contributor.author | 江豐任 | zh_TW |
dc.date.accessioned | 2021-07-11T15:23:46Z | - |
dc.date.available | 2022-02-13 | |
dc.date.copyright | 2019-02-13 | |
dc.date.issued | 2019 | |
dc.date.submitted | 2019-01-28 | |
dc.identifier.citation | G. Huang, et al., 'A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications,' in IEEE Journal of Solid-State Circuits, vol. 47, no. 11, pp. 2783-2795, Nov. 2012.
S. Hsieh, et al., 'A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC,' 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, 2016, pp. 1-2. Y. Chung, et al., 'A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS,' in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 1, pp. 10-18, Jan. 2015. M. Liu, et al., 'A 7.1-fJ/Conversion-Step 88-dB SFDR SAR ADC With Energy-Free “Swap To Reset”,' in IEEE Journal of Solid-State Circuits, vol. 52, no. 11, pp. 2979-2990, Nov. 2017. H. Tai, et al., 'A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS,' 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 196-197. Y. Hu, et al., 'An 89.55dB-SFDR 179.6dB-FoMs 12-bit 1MS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration, ' 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), Tainan, 2018, pp. 253-256. W. Liu, et al., 'A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration,' in IEEE Journal of Solid-State Circuits, vol. 46, no. 11, pp. 2661-2672, Nov. 2011. Yuan Zhou, et al., 'A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration,' 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, 2014, pp. 1-2. W. Tseng, et al., 'A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters,' in IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2222-2231, Oct. 2016. D. Chang, et al., 'Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC,' in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 2, pp. 322-332, Feb. 2017. C. C. Lee, et al., 'A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS,' 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, 2015, pp. C62-C63. T. Miki, et al., 'A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques,' in IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1372-1381, June 2015. P. Harpe, et al., 'An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR,' 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 194-195. P. Harpe, et al., 'A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step,' in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3011-3018, Dec. 2013. M. van Elzakker, et al., 'A 10-bit Charge-Redistribution ADC Consuming 1.9μW at 1 MS/s,' in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010. F. van der Goes, et al., 'A 1.5 mW 68 dB SNDR 80 Ms/s 2×Interleaved Pipelined SAR ADC in 28 nm CMOS,' in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2835-2845, Dec. 2014. Masaya Miyahara, et al., 'A low-noise self-calibrating dynamic comparator for high-speed ADCs,' 2008 IEEE Asian Solid-State Circuits Conference, Fukuoka, 2008, pp. 269-272. S. Babayan-Mashhadi, et al., 'Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 343-352, Feb. 2014. Y. Zhu, C. Chan, et al., 'An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS,' in IEEE Journal of Solid-State Circuits, vol. 51, no. 5, pp. 1223-1234, May 2016. B. Sung, et al., 'A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration,' 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, 2013, pp. 281-284. W. Li, et al., 'A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator,' 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, 2017, pp. 225-228. C. Liu, et al., 'A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,' in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010. S. M. Chen, et al., 'A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μmCMOS,' in IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006. Y. Hu, et al., 'A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique,' 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, 2016, pp. 149-152. V. Hariprasath, et al., 'Merged capacitor switching based SAR ADC with highest switching energy-efficiency,' in Electronics Letters, vol. 46, no. 9, pp. 620-621, 29 April 2010. F. Kuttner, 'A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS,' 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), San Francisco, CA, USA, 2002, pp. 176-177 vol.1. C. Liu, et al., 'A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,' 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, 2010, pp. 386-387. B. P. Ginsburg, et al., '500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC,' in IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 739-747, April 2007. R. Kapusta, et al., 'A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS,' 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, 2013, pp. 472-473. M. J. Kramer, et al., 'A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS,' in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2891-2900, Dec. 2015. M. Shim, et al., 'An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC,' 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, 2016, pp. 1-2. J. Zhong, et al., 'A 12b 180MS/s 0.068mm2With Full-Calibration-Integrated Pipelined-SAR ADC,' in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 7, pp. 1684-1695, July 2017. S. Hsieh, et al., 'A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator,' 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 240-242. J. Shen, et al., 'A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS,' 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C282-C283. Z. Ding, et al., 'A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based Comparator,' 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, 2018, pp. 93-94. H. Huang, et al., 'A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer,' in IEEE Journal of Solid-State Circuits, vol. 52, no. 6, pp. 1551-1562, June 2017. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78847 | - |
dc.description.abstract | 類比至數位轉換器可以將自然界類比訊號轉換成數位訊號提供數位處理器做分析。本論文提出一個操作在0.9伏特電壓每秒一百萬次取樣的十四位元連續漸進式類比至數位轉換器,實現於40奈米製程。
本電路使用次區間電路架構,配合偵測與迴避切換及同步切換來降低電容陣列的切換能量消耗,並使用追蹤切換的平均技巧提升對比較器雜訊的抵抗性及能量效率。由於縮小電容能減少電容切換能量,為了解決嚴重的電容誤差,還有偵測與迴避切換的架構限制,使用分離式權重補償技巧可以完美克服權重補償的瓶頸。且次區間電路架構存在著比較器之間的電壓平移誤差,背景平移誤差校正能追蹤誤差量,並回傳至類比電路做校正來降低平移誤差造成的影響和次電路比較器的能量消耗。 本文提出的類比至數位轉換器在每秒一百萬次取樣速度下,功率消耗為8.38瓦特。校正後,差動非線性和積分非線性分別為0.51/-0.54和1.34/-1.31最低有效位元。量測得到的有效位元最高可達到12.55的有效位元,訊號對雜訊及諧波比分別為77.3dB和101.38dB,Schreier品質因數為185.1dB。 | zh_TW |
dc.description.abstract | An analog-to-digital converter (ADC) can convert analog signal in nature to digital signal for digital-signal-processor (DSP). The thesis present a 0.9V 1MS/s 14-bit successive-approximation register (SAR) analog-to-digital converter (ADC) fabricated in 40 nm CMOS.
The design is a sub-ranging SAR ADC architecture. With detect-and-skip (DAS) and align switching method, it can reduce switching energy in capacitor array. Also, tracking average technique can suppress input-referred noise and power consumption of comparator. To solve capacitor mismatch because of small unit capacitor for saving switching power and the restriction of DAS architecture, weight-split compensation overcomes the bottleneck of weight compensation. The proposed background offset mismatch calibration can track the offset mismatch in sub-ranging ADC and adjust capacitor array voltage to solve this problem and save coarse comparator power. The proposed ADC consumes 8.38μW at a sampling-rate of 1 MS/s. After calibration, DNL and INL are 0.51/-0.54 and 1.34/-1.31 LSB. The measured ENOB can reach 12.55-bit, with SNDR and SFDR are 77.3dB and 101.38dB. FoMS are 185.1 dB. | en |
dc.description.provenance | Made available in DSpace on 2021-07-11T15:23:46Z (GMT). No. of bitstreams: 1 ntu-108-R05943018-1.pdf: 2533462 bytes, checksum: 432c2cbc4982a7419fcd87ef552b1211 (MD5) Previous issue date: 2019 | en |
dc.description.tableofcontents | 口試委員會審定書 I
致謝 II 摘要 III Abstract IV Contents V List of Figures VII List of Tables X Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converter 3 2.1 Introduction 3 2.2 Static Performance 3 2.2.1 Offset Error 3 2.2.2 Gain Error 4 2.2.3 Differential and Integral Nonlinearity (DNL and INL) 5 2.3 Dynamic Performance 6 2.3.1 Signal-to-Noise Ratio (SNR) 6 2.3.2 Total Harmonic Distortion (THD) 7 2.3.3 Spurious-Free Dynamic Range (SFDR) 7 2.3.4 Signal-to-Noise and Distortion Ratio (SNDR) 8 2.3.5 Effective Number of Bits (ENOB) 8 2.3.6 Figure of Merit (FoM) 8 2.4 ADC Architectures 9 2.4.1 Successive-Approximation-Register (SAR) Architecture 9 2.4.2 Time-Interleaved Architecture 11 2.4.3 Pipeline Architecture 12 2.4.4 Two-Step and Sub-Ranging Architecture 13 Chapter 3 High-Resolution and Low-Power SAR ADC 14 3.1 Introduction 14 3.1.1 Conventional SAR ADC Design 15 3.1.2 Bottleneck of SAR ADC 17 3.2 High Resolution DAC Design 18 3.2.1 Design Considerations 19 3.2.1.1 Settling Error 19 3.2.1.2 Sampling Noise 21 3.2.1.3 Capacitor Mismatch 21 3.2.2 Capacitor Calibration 24 3.3 Comparator Design 27 3.3.1 Noise 31 3.3.2 Offset 33 3.4 Offset Calibration 34 3.6 Summary 37 Chapter 4 A 14-bit 1MS/s Sub-Ranging SAR ADC with Digital Calibration 38 4.1 Introduction 38 4.2 Proposed Architecture 40 4.3 High Efficiency Switching 42 4.3.1 Detect-and-Skip (DAS) Algorithm 42 4.3.2 Aligned Switching Technique 47 4.4 Weight Compensation Algorithm 48 4.4.1 Non-Skipping Weight Compensation 49 4.4.2 Weight-Split Compensation 51 4.4.3 Capacitor Calibration 54 4.5 SNR Enhancement 57 4.5.1 Tracking Average 57 4.5.1 Low-Noise Comparator 59 4.6 Offset Mismatch Calibration 63 4.6.1 Digital Detection and Tracking 64 4.6.2 Analog Adjustment 67 4.7 Digital System 71 Chapter 5 Experiments Results 73 5.1 Measurement Environment 73 5.2 Measurement Results 74 Chapter 6 Conclusions 81 Bibliography 82 Appendix 88 | |
dc.language.iso | zh-TW | |
dc.title | 全數位校正的高解析度連續漸進式類比至數位轉換器 | zh_TW |
dc.title | All Digital Calibration for High-Resolution Successive-Approximation Register Analog-to-Digital Converter | en |
dc.type | Thesis | |
dc.date.schoolyear | 107-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),戴宏彥(Hung-Yen Tai) | |
dc.subject.keyword | 連續漸進式,類比至數位轉換器,偵測與迴避切換,同步切換,追蹤切換平均,分離式權重補償,背景平移誤差校正, | zh_TW |
dc.subject.keyword | successive-approximation register (SAR),analog-to-digital converter (ADC),detect-and-skip and aligned switching,tracking average,weight-split compensation,background offset mismatch calibration, | en |
dc.relation.page | 89 | |
dc.identifier.doi | 10.6342/NTU201900262 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2019-01-28 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-108-R05943018-1.pdf 目前未授權公開取用 | 2.47 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。