應用於互補式金屬氧化物半導體微機電製程平台之無接合封裝技術

Abstract

本論文目的為在CMOS-MEMS 0.35-μm 2P4M製程平台上開發適用於晶圓級無接合晶片封裝技術。本技術主要透過CMOS金屬層的堆疊組合，將上方金屬層作為釋放孔洞設計，下方金屬層作為元件結構設計，結構濕蝕刻完成釋放後，最後以金屬蒸鍍搭配遮罩將釋放孔洞填滿並完成封裝。 此處使用了鍺金屬(Ge)和聚對二甲苯(Parylene-C)，兩種材料作為結構封裝使用。在蒸鍍了1.5 μm厚的鍺金屬後，將其放置於真空腔體內量測並抽氣降低壓力至2×10-6 Torr，經長時間觀測約78小時，其共振尖峰沒有顯著改變，代表鍺金屬可以隔絕結構空腔壓力和外界壓力。 另一方面，沉積非金屬材料聚對二甲苯，可以省去遮罩直接進行沉積，在沉積了2.1 μm厚的聚對二甲苯後，將釋放孔洞填滿並完成封裝，因為共振器結構亦被包覆而導致其共振頻率改變，但是此薄膜亦可以隔絕結構空腔內外壓力，當外界壓力改變亦不會影響內部結構運行。 釋放孔洞設計具有額外優點─在濕蝕刻的過程中有效達到擴散控制的效果並提高製程良率。在3×3 μm2的釋放孔洞設計的結構，可將蝕刻時成功釋放結構的可容忍過蝕刻時間變成10倍長。此釋放孔洞結構設計可以有效改善在CMOS-MEMS製程平台上以鋁金屬作為結構，二氧化矽作為犧牲層的結構在濕蝕刻後製程上產生的良率問題。

The purpose of this thesis is to develop a zero-bonding chip packaging technology on the CMOS-MEMS 0.35-μm 2P4M process platform. In particular, this technology uses the stacking combination of metal layers in the CMOS process to form both the packaging cover and the device structures. With proper release hole design on the packaging cover, the structure is released using wet etching process followed by a re-fill process to seal the release holes. Here, the refill process utilizes two approaches: metal evaporation of Ge and va-por deposition of parylene-C. For the case of Ge metal, the released structure was de-posited with a 1.5 μm thick Ge and measured in a vacuum chamber pumped down to a pressure of 2×10-6 Torr. The measured frequency transmission presents a resonance peak similar to that at atmosphere. The resonance peak did not change significantly during about 78 hours staying in the vacuum chamber, indicating that the Ge thin film successfully isolates the structure cavity and the external pressure. On the other hand, the non-metallic material parylene-C was deposited directly without the shadow mask. With a 2.1-μm parylene, the release holes are completely filled and the resonator structure is also coated with parylene, which causes the reso-nance frequency to change. Similar to the Ge case described above, parylene refilling can also isolate the internal and external pressure of the structure cavity, and when the external pressure changes, it will not affect the operation of the internal structure. The release hole design has an additional advantage—controlling the diffusion path during the wet etching process and in turn improving the release process yield. In particular, the structure covered with release holes can sustain the over-etch for 10× longer, from 5 min to 50 min, in the etchant compared to a reference device with no cover. This release hole structure design provides an effective approach to improving the yield problem of metal-rich CMOS-MEMS based devices.