次十奈米鐵電場效電晶體與高介電係數閘極介電層之原子層工程之研究

Abstract

隨著摩爾定律的快速演進至3奈米技術節點，電晶體尺寸微縮已逼近極限，其中功率損耗及短通道效應的問題已越來越嚴重，因此新穎製程的開發以及新材料的研究正廣泛地進行中，其中原子層沉積(atomic layer deposition, ALD)在半導體製程中成為關鍵性的技術。現在有很多方法已經提出作為替代方案，以避免快速的尺寸微縮所帶來的問題，例如垂直電晶體、奈米線通道疊層、鐵電負電容材料及二維材料，以期能夠延續摩爾定律。其中為了能夠定義更小的特徵尺寸，傳統的有機光阻也面臨到尺寸微縮的問題，在本論文中，我們除了應用原子層沉積衍生之技術提高薄膜品質外，也應用了無機光阻hydrogen silsesquioxane(HSQ)搭配氦離子束顯微鏡(Helium ion microscope)，成功的定義出次10奈米的圖形，並進一步用其來探討電晶體中的短通道效應。 鐵電負電容(ferroelectric negative capacitance)材料被認為是能夠抑制短通道效應(short channel effects)的解決方案之一，本論文使用次10奈米微影技術製作閘極長度為8奈米的電晶體，探討使用高品質鐵電材料二氧化鉿鋯(Hf0.5Zr0.5O2, HZO)薄膜作為閘極介電層，是否能夠抑制短通道效應。其中HZO薄膜的鐵電與負電容特性由金屬/鐵電/金屬(metal-ferroelectric-metal)及金屬/鐵電/介電質/半導體(metal-ferroelectric-insulator-semiconductor)電容結構搭配脈衝模組進行量測，由殘餘極化(remanent polarization)及電容-電壓磁滯(capacitance-voltage hysteresis)特性結果得知HZO薄膜有優異鐵電特性。相較於一般使用順電材料作為閘極介電層的電晶體，使用HZO鐵電薄膜作為閘極介電層的電晶體，其次臨界襬幅(subthreshold swing)成功的被抑制低於60 mV/dec，且漏電流也被抑制了2個數量級，成功的達到低功耗的要求。 此外，在高介電係數閘極氧化層的沉積技術方面，本論文使用了原子層轟擊技術(atomic layer bombardment, ALB)提升閘極氧化層的品質，使用逐層(layer-by-layer)、原位(in situ)氦氣/氬氣混和電漿(He/Ar plasma)處理，使介電層的密度上升 (densification)並減少其中的氧空缺和缺陷，藉由金屬/氧化物/半導體(metal-oxide-semiconductor)及金屬/氧化物/金屬(metal-oxide-metal)電容量測結果得知，原子層轟擊技術使得高介電係數閘極氧化層的介電常數上升了約11%，且其漏電流下降了3個數量級，實現了提升閘極的電容值並降低了其功率損耗，有助於此技術於先進邏輯元件之應用。

With the rapid evolution of the Moore's law to the 3nm technology node, the size reduction of nanoscale transistors has approached the limit. The power consumption and the short channel effects have become severe problems for further feature size shrinking. Therefore, new processing techniques and novel materials are widely investigated. Hence atomic layer deposition (ALD) has been proposed as one of the key technology for preparing high-quality nanoscale thin films in advanced semiconductor fabrication. In order to define smaller feature sizes, traditional organic photoresists also face the difficulties. In this thesis, advanced ALD technique was developed to improve the quality of the nanoscale thin fims. In addition, the helium ion microscope (HIM) together with the inorganic photoresist hydrogen silsesquioxane (HSQ) was used to define sub-10 nm patterns for the investigation of short channel effects in nanoscale transistors. Ferroelectric negative capacitance has been considered to be one of the solutions that can suppress short channel effects. In this thesis, nanoscale ferroelectric transistors were demonstrated with high-quality ferroelectric hafnium zirconium dioxide (Hf0.5Zr0.5O2, HZO) as the gate dielectric. In addition, the gate length of the ferroelectric transistors was scaled down to ~8 nm, which was defined by the HIM technique along with the HSQ resist. The polarization-voltage (P-V) and capacitance-voltage (C-V) characteristics of the metal-ferroelectric-metal (MFM) and metal-ferroelectric-insulator-semiconductor (MFIS) capacitors reveal that the HZO film exhibited excellent ferroelectric properties. In addition, a time-domain analysis indicates that the transient negative capacitance effect takes place in the FE gate dielectric. As compared with the paraelectric HfO2 gate dielectric, the ferroelectric HZO gate dielectric contributes to a suppression of the off current by ~2 orders of magnitude and a decrease of subthreshold swing below 60 mV/dec, along with an enhancement of the on/off ratio in the reverse sweep direction in nanoscale transsitors. In the last part of this thesis, the atomic layer bombardment (ALB) technique was proposed to enhance the qualities of the high-K gate dielectric. The layer-by-layer, in situ helium/argon mixture plasma treatment was performed in each ALD cycle to increase the film density and reduce the oxygen vacancies/defects in the gate dielectric. The electrical characterizations show that the dielectric constant of the high-K gate dielectric was increased by ~11% and the gate leakage current was suppressed by 3 orders of magnitude, which demonstrates that the ALB technique is highly effective to enhance the dielectric properties of nanoscale thin films.