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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳志毅 | zh_TW |
| dc.contributor.advisor | Chih-I Wu | en |
| dc.contributor.author | 郭勝文 | zh_TW |
| dc.contributor.author | Sheng-Wen Kuo | en |
| dc.date.accessioned | 2021-07-11T15:02:40Z | - |
| dc.date.available | 2024-08-20 | - |
| dc.date.copyright | 2019-08-26 | - |
| dc.date.issued | 2019 | - |
| dc.date.submitted | 2002-01-01 | - |
| dc.identifier.citation | [1] S. M. S. Jagan Singh Meena, Umesh Chand & Tseung-Yuen Tseng, "Overview of emerging nonvolatile memory technologies," Nanoscale Research Letters, 2014, doi: 10.1186/1556-276X-9-526.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78537 | - |
| dc.description.abstract | 電阻式記憶體具有高存取速度、低操作電壓、良好的耐久性、長的記憶維持時間、構造簡單且具備尺寸微縮的特性,其諸多優點吸引許多研究團隊投入研究。再者由於肌膚電子與可撓性顯示器的新興應用,對可撓性、可折疊的需求不斷增加,因此,我們欲開發電阻式記憶體具備高可撓性。
本論文以具離子特性及層狀結構的碘化鉍作為電阻切換層,為了驗證碘化鉍構成電阻式記憶體與現今IC技術兼容,將此碩論分為兩部份進行深入探討。第一部分,為了將碘化鉍與矽結合應用,我們選用高摻雜的矽基板作為我們底部電極,且採用自組裝層ODTS修飾基板表面,解決基板表面的懸浮鍵與晶格不匹配的問題。藉由掃描式電子顯微鏡、原子力顯微鏡和X射線繞射分析儀顯示了碘化鉍沉積在經ODTS修飾的矽基板,在c軸方向有較高的晶格指向使表面平整均勻;然而碘化鉍沉積在矽基板結晶會呈片狀,且由於不規則的晶格指向使得表面較為粗糙。由於不同結晶面的碘化鉍接觸基板且具有各向異性的載子遷移率,因此ODTS元件在高阻態時電流傳導是被蕭特基傳輸所主導;而矽元件在高阻態時電流傳導主要以空間電荷為主導,由於ODTS增加了能障寬度以及沿垂直晶面的導電性較低,使得ODTS元件有較高的on/off ratio為10^9且能實現多階段的資料存取,與矽元件對比,ODTS元件有優異的耐久性與長的記憶維持性,最後在XPS組成物分析中發現了碘離子在電場的作用下遷移,因此碘離子為電阻切換發生的關鍵。 在第二部分,我們發現了元件若以Pt作為底部電底,則一開始需要負偏壓使電阻切換,另一方面,選用石墨烯/銅箔作為底部電極起初不需要施加較大的偏壓使導電燈絲形成,並且操作電壓set與reset僅需為0.3V與-0.2V。為了研究絕緣材料碘化鉍沉積在不同金屬電極上的差異,因此將不同厚度的碘化鉍以不同金屬做為基底藉由XPS分析元素組成與化學狀態,結果我們在金屬電極上發現自形成的金屬鉍的訊號,這使得離子遷移所需的活化能降低,說明了以碘化鉍作為電阻切換,導電燈絲的形成是由於碘離子遷移引起鉍價電荷減少。接著為了增加記憶窗口,利用絕緣層h-BN減少漏電流且將on/off ratio提升至10^6以上。最後是元件的彎曲測試,證明了元件以銅箔作為底部電極具有優異的可撓性並且進行了彎曲測試,元件Au/BiI3/graphene/Cu foil 以曲率半徑8.75mm 進行彎曲穩定度測試,當中彎曲了5000 次仍其高低阻電阻值比值約為10^4 ;而將元件Au/BiI3/h-BN/Cu foil 以不同曲率半徑8.75mm、7.75mm、6.25mm、5mm 進行彎曲穩定度測試,其高低阻電阻值比值依然能保持約為10^6 維持穩定的元件特性。 | zh_TW |
| dc.description.abstract | Resistive random access memory (RRAM) with features of high switching, low operation voltage, good endurance, long retention, simple structure, and excellent scalability has attractive numerous research groups to devote themselves to this emerging memory. In addition, there has been an increasing demand for flexible, foldable and twistable memory due to the emerging application of skin electrons and flexible display. Therefore, they motivate us to investigate resistive switching memory with high flexibility.
In this thesis, BiI3 with ionic and layered structure was used as resistive switching layer. To demonstrate the compatibility of BiI3 based RRAM with silicon IC technology, the thesis can be divided into two parts. In the first part, to integrate BiI3 with silicon, the heavily degenerated silicon was used as bottom electrode. To ease the surface dangling bonds of the silicon and the mismatch of lattice constant between the substrate and silicon, self-asssembled monolayer of octadecyltrichlorosilane (ODTS) was employed as buffer layer. With the results of scanning electron microscope (SEM), atomic force microscope (AFM), and X-ray diffraction pattern (XRD), they revealed that the BiI3 crystals on the ODTS/silicon substrate had highly c-axis orientation, giving rise a flatten and smooth surface of the BiI3 film. While the BiI3 crystals on the bare silicon substrate is the form of plate, they randomly orientated and caused a rough surface. Due to different facet of BiI3 crystals contact to the substrate and anisotropic carrier mobility, the current conduction mechanism of the device on the ODTS substrate (the ODTS device) at high resistance state is dominated by Schottky contact and that of the devices on the bare Silicon (the Si devices) is dominated by space charge limited conduction. Due to ODTS layer (increasing the tunneling width) and low conductivity in out-of-plane direction of the BiI3 crystal, the devices demonstrated much high on/off ratio of 10^9 enabling the multilevel storage. In contrast to the Si devices, the ODTS devices have excellent endurance under consecutive voltage sweeping and long retention over 10^5s. In the experiments of X-ray photoemission spectroscopy (XPS), it reveals that the iodide ion would migrate under electrical field. And, it plays a key role in the resistive switching. In the second part, the RRAM with the structure of metal/BiI3/metal were fabricated. We found that the resistive switching devices using Pt as bottom electrode require a negative forming bias. On the other hand, the devices using the graphene/copper foil as bottom electrode do not need the forming step. And the set/reset voltage for the device using metal electrode is quite low and is 0.3/-0.2V, respectively. To study the difference of the insulating layer of BiI3 on different metal electrode, X-ray photoemission spectroscopy was used to study the stoichiometry and chemical state of different thickness of BiI3 on different metal substrates. As a result, self-forming metallic bismuth was observed in the BiI3 on the metal electrode, which lowers the activation energy of ion migration. It suggests that the origin of resistive switching in the BiI3 devices is the reduction of valence charge of bismuth induced by migration of iodide ion which formed a conductive path. To enlarge the operating window, the insulating h-BN layer is applied suppress the leakage current and further promote on/off ratio to 10^6. The device using copper foil demonstrated the high flexibility and the bending tests were carried out. The Au/BiI3/graphene/Cu foil on/off ratio still maintained at 10^4 after bending 5000 times. The Au/BiI3/h-BN/Cu foil device was tested for bending stability with different radius of curvature 8.75 mm, 7.75 mm, 6.25 mm, and 5 mm, and on/off ratio maintain about 10^6. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-11T15:02:40Z (GMT). No. of bitstreams: 1 ntu-108-R06941065-1.pdf: 7368431 bytes, checksum: 950b170cdf237918db60f9abf774e642 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 誌謝 I
中文摘要 III ABSTRACT V CONTENTS VIII 圖目錄 XII 表目錄 XVII Chapter 1 緒論 1 1.1 記憶體簡介 1 1.1.1 前言 1 1.1.2 揮發性記憶體 1 1.1.3 非揮發性記憶體 3 1.1.4 困難與挑戰 4 1.2 次世代非揮發性記憶體 5 1.2.1 鐵電式隨機存取記憶體 (Ferroelectric RAM,FeRAM) 5 1.2.2 相變化隨機存取記憶體(PCRAM) 7 1.2.3 磁阻式隨機存取記憶體 (MRAM) 8 1.2.4 電阻式隨機存取記憶體 (RRAM) 10 1.3電阻式隨機存取記憶體原理 11 1.3.1 RRAM結構介紹 11 1.3.2 熱燈絲切換理論(Filament Switching Mechanism) 14 1.3.3 介面切換理論(Interface-Type Switching Mechanism) 15 1.3.4 電荷缺陷捕捉理論(Charge trapping/detrapping) 18 1.4 絕緣層載子傳導機制 19 1.4.1 傳導機制 19 1.4.2 Electrode Limited conduction mechanism 20 1.4.3 Bulk Limited conduction mechanism 22 1.5 二維材料 26 1.5.1 二維材料介紹 26 1.5.2 石墨烯簡介 28 1.6 研究動機 31 Chapter 2 實驗原理與方法 32 2.1 實驗理論與原理 32 2.1.1 凡德瓦磊晶(Van der waals epitaxy) 32 2.1.2 RRAM 電性量測 33 2.2 實驗製程儀器 35 2.2.1 氮氣手套箱 35 2.2.2 化學氣相沉積(Chemical Vapor Deposition, CVD) 36 2.2.3 氧電漿蝕刻機 36 2.2.4 真空熱蒸鍍機 37 2.3 量測分析 38 2.3.1 拉曼光譜分析 38 2.3.2 原子力顯微鏡 40 2.3.3 X射線繞射分析儀 41 2.3.4 掃描式電子顯微鏡(Scanning Electron Microscope, SEM)及X射線能量散怖分析儀 42 2.3.5 紫外光與X射線光電子能譜(UPS&XPS) 44 2.4 實驗材料介紹 46 2.5 實驗流程 49 2.5.1 以矽基板作為底部電極 49 2.5.2 以金屬作為底部電極 51 Chapter 3 BiI3沉積於剛性基板 53 3.1 實驗動機 53 3.2 表面分析 54 3.3 電性分析 56 3.2.1 BiI3 on ODTS/Si 56 3.2.2 BiI3 on Si 61 3.4 結構參數 65 3.5.1電極大小 65 3.4.2不同厚度 68 3.4.3不同鍍率 69 3.5 光譜特性分析 74 Chapter 4 BiI3沉積於金屬電極 76 4.1 實驗動機 76 4.2上電極 79 4.3底部電極 80 4.3.1 表面分析 80 4.3.2 電性量測 81 4.4 可撓性記憶體 81 4.4.1 表面分析 81 4.4.2 電性分析 82 4.4.3光譜特性分析 85 4.4.4 彎曲穩定度測試(bending test) 86 Chapter5 總結與未來展望 88 5.1總結 88 5.2未來展望 90 Reference 91 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 可撓性記憶體 | zh_TW |
| dc.subject | 導電燈絲 | zh_TW |
| dc.subject | 自組裝層 | zh_TW |
| dc.subject | 碘化鉍 | zh_TW |
| dc.subject | 電阻式記憶體 | zh_TW |
| dc.subject | 凡得瓦磊晶 | zh_TW |
| dc.subject | 化學氣相沉積 | zh_TW |
| dc.subject | RRAM | en |
| dc.subject | Bismuth triiodide | en |
| dc.subject | self-assembled monolayer | en |
| dc.subject | conductive filament | en |
| dc.subject | Van der waals epitaxy | en |
| dc.subject | Chemical vapor deposition | en |
| dc.subject | flexible memory | en |
| dc.title | 二維材料碘化鉍於凡得瓦介面之非揮發性電阻式記憶體與其可撓性應用 | zh_TW |
| dc.title | Nonvolatile resistive switching memory with two dimensional material of bismuth iodide on van der waals surface and its flexible application | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 107-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 林恭如;吳肇欣;曾賢德 | zh_TW |
| dc.contributor.oralexamcommittee | Gong-Ru Lin;Chao-Hsin Wu;Shien-Der Tzeng | en |
| dc.subject.keyword | 電阻式記憶體,碘化鉍,自組裝層,導電燈絲,凡得瓦磊晶,化學氣相沉積,可撓性記憶體, | zh_TW |
| dc.subject.keyword | RRAM,Bismuth triiodide,self-assembled monolayer,conductive filament,Van der waals epitaxy,Chemical vapor deposition,flexible memory, | en |
| dc.relation.page | 97 | - |
| dc.identifier.doi | 10.6342/NTU201903879 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2019-08-18 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 光電工程學研究所 | - |
| dc.date.embargo-lift | 2029-12-31 | - |
| 顯示於系所單位: | 光電工程學研究所 | |
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