上閘極二維過渡金屬硫族化物電晶體之高介電係數 金屬閘極堆疊之研究

Abstract

本論文中，我們製造了上閘極過渡金屬二硫化物電晶體，並透過原子層沉積技術沉積閘極介電層。第一部分討論了原位原子層摻雜技術用於精確控制鉿摻雜入氮化鈦中間層，以調控鉑/氮化鈦鉿雙層金屬閘極堆疊的等效功函數。鉑/氮化鈦鉿雙層金屬閘極堆疊的等效功函數，可藉由插入摻有鉿的氮化鈦中間層，使之在4.54 eV至5.17 eV的範圍內調控，以代替單層鉑閘電極的等效功函數(~5.7 eV)。結果顯示：原位原子層摻雜技術可以有效調控金氧半電容元件中的金屬閘極之功函數。 第二部分探討在過渡金屬二硫化物上，使用原子層沉積技術成長均勻的次10奈米高介電係數介電層的成核工程。在這一部分中，由於已有許多材料在二硫化鉬進行成核工程研究，因此我們選擇二鍗化鉬作為過渡金屬二硫化物材料，成功在二維二鍗化鉬上，透過臭氧基製程、氮化鋁插入層和低溫物理吸附的原子層沉積製程來製備成核層，實現了連續、均勻且厚度低於10奈米的氧化鋁高介電係數電介質。成核層的存在使得次10奈米氧化鋁高介電係數電介質的漏電流明顯降低。然而，X射線光電子能譜顯示臭氧基製程會造成二鍗化鉬的氧化，這對於二鍗化鉬的電性是有害的。對於氮化鋁插入層而言，X射線光電子能譜顯示在沒有鉬-氧鍵的生成，但形成了鉬-氮鍵，且在鍗-3d能级也沒有出現化學位移，這表示氮化鋁插入層不會造成二鍗化鉬的氧化。用低溫物理吸附成核層覆蓋的二鍗化鉬，其X射線光電子能譜則與使用機械剝離法所製備的二鍗化鉬相同，這顯示了在低溫物理吸附的過程中沒有發生任何化學反應。結果顯示，低溫物理吸附和氮化鋁插入層製備的成核層，對於在二鍗化鉬電晶體上的成長高品質高介電係數介電層是有效且良好的方法。 在過渡金屬二硫化物上成功沉積連續、均勻和低於10奈米的氧化鋁高介電係數介電層後，我們在第三部分中製作了上閘極次10奈米高介電係數介電層的過渡金屬二硫化物電晶體。在這一部分中，我們分別使用現今製程較為成熟的兩種過渡金屬二硫化物：二硫化鉬與二硫化鎢，作為過渡金屬二硫化物通道材料。次10奈米高介電係數閘極介電層對於過渡金屬二硫化物電晶體而言，至關重要，研究結果顯示具有低溫成核層的次10奈米氧化鋁閘極介電層，可以顯著抑制閘極漏電流，並且不會發生氧化反應。利用高品質的次10奈米氧化鋁高介電係數閘極介電層，在上閘極二硫化鉬與二硫化鎢電晶體中，皆得到了低閘極漏電流以及低次臨界擺幅。 最後，我們整合鐵電負電容進入過渡金屬二硫化物場效電晶體的上閘極結構。在本論文最後一部分中，遠程電漿原子層沉積技術將用來實現不需退火製程，就呈現出鐵電性質的氧化鋯鉿薄膜。這是成功製作過渡金屬二硫化物負電容場效電晶體的一個重要因素，因為通常需要後退火製程(約600~1000°C)才能獲得具有鐵電性質的氧化鋯鉿薄膜，此溫度高於二硫化鎢的穩定溫度。透過使用具有鐵電性質的氧化鋯鉿薄膜，呈現出過渡金屬二硫化物負電容場效電晶體的性質，並展示了次臨界擺幅的改善。

In this thesis, top-gated transition metal dichalcogenides (TMD) transistor was fabricated. The gate dielectric was deposited by Atomic Layer Deposition (ALD). The in In this thesis, top-gated transition metal dichalcogenides (TMD) transistor was fabricated and investigated. The high-K gate dielectrics were prepared by atomic layer deposition (ALD). The in-situ atomic layer doping technique was studied in the first part, which was used to precisely control the Hf doping percentage into the thin TiN interlayer for tailoring the effective work function (EWF) of the Pt/TixHfyN bilayer metal gate stack. As compared with the EWF (~5.7 eV) of the single-layer Pt gate electrode, the EWF of the Pt/TixHfyN bilayer metal gate stacks is tunable with the range from 4.54 eV to 5.17 eV by the insertion of the thin TixHfyN interlayer. The result indicates that the in-situ atomic layer doping technique is an effective approach to modulate the EWF of metal gate in future MOS devices. In the second part of this thesis, we report the nucleation engineering for atomic layer deposition of uniform sub-10 nm high-K gate dielectrics on TMD. Continuous, uniform, and sub-10nm Al2O3 high-K dielectrics upon two-dimensional MoTe2 are realized by ALD based on a nucleation layer (NL) prepared by the ozone-based process, interfacial AlN, and low-temperature (low-T) physical adsorption. The NLs gives rise to significant reduction of the leakage current in the sub-10nm Al2O3 high-K gate dielectrics. However, X-ray photoelectron spectroscopy (XPS) reveals the oxidation of MoTe2 as the NL was prepared by the ozone-based process, which is detrimental to the electrical properties of MoTe2. As for the AlN NL, the Mo−N bonds were formed without the presence of the Mo-O bonds and no chemical shift appeared in Te-3d XPS spectrum, indicating the AlN NL did not result in the MoTe2 oxidation. The XPS spectra of MoTe2 covered with the low-T NL is the same as those of the as-exfoliated MoTe2 flake, revealing the absence of chemical reactions during low-T physical adsorption. The result demonstrates that the NLs prepared by the low-T physical adsorption and the interfacial AlN are effective and favorable for the high-quality high-K gate dielectrics on MoTe2. With successful deposition of continuous, uniform, and sub-10nm Al2O3 high-K gate dielectrics upon TMD, top-gated TMD transistors with sub-10nm high-K gate dielectrics were fabricated and characterized using MoS2 and WS2 as the TMD channel materials, respectively. The results reveal significant suppression of the gate leakage current in the sub-10 nm Al2O3 gate dielectrics with the nucleation layer prepared by the low-T physical adsorption method. No oxidation occurred during the deposition of the low-temperature Al2O3 nucleation layer on MoS2 and WS2. With the high-quality sub-10nm Al2O3 high-K gate dielectrics, low gate leakage current and low subthreshold swing were demonstrated on both the top-gated MoS2 and WS2 transistors. Finally, ferroelectric negative capacitance (NC) material was integrated into the gate stack of top-gated TMD transistors. The remote plasma atomic layer deposition was used to achieve the ferroelectricity in as-deposited HfZrO2 (HZO) thin films without any post-annealing treatment. This is an important for the TMD NC transistors since the post-annealing process at ∼600–1000 °C was usually required to obtain ferroelectric HZO thin films, which is detrimental to WS2. This ferroelectric HZO thin film leads to demonstration of the top-gated WS2 NC transistors with the improvement in the subthreshold swing.