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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78336完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳宗霖(Tzong-Lin Wu) | |
| dc.contributor.author | Chin-Yi Lin | en |
| dc.contributor.author | 林晉毅 | zh_TW |
| dc.date.accessioned | 2021-07-11T14:51:50Z | - |
| dc.date.available | 2025-08-03 | |
| dc.date.copyright | 2020-08-04 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-08-03 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78336 | - |
| dc.description.abstract | 在高速差動傳輸介面中，電磁干擾、射頻干擾以及靜電放電防護是非常重要的議題。當實際系統產生的共模雜訊經過連接器及轉接線等不連續處時，輻射雜訊將會被激發，干擾外部系統或系統內的無線模組。由外部產生的靜電放電，經由輸入輸出介面進到電子系統中，可能會對內部的元件或模組產生嚴重的傷害。為了解決上述高速差動傳輸介面中所面臨的問題，共模雜訊抑制及靜電防護技術已在數十年間大量發展。 本文中首先提出一設計方法，用以合成反射式及吸收式共模雜訊濾波器。兩種設計都實現在積體被動元件製程，展現極高的差模截止頻率及極小的面積768 × 724平方微米。反射式設計展現從2.4吉赫至12.0吉赫的共模雜訊抑制，吸收式設計則在3.0吉赫至4.0吉赫內吸收80%的共模雜訊，並在3.5吉赫達到97.2%的吸收峰值。 由於靜電防護元件及共模雜訊濾波器在高速差動輸入輸出介面中有關鍵作用，本文接著提出兩元件之共設計，共模等效電路類似橢圓低通濾波器。其中一級設計在2.22吉赫至2.76吉赫內抑制共模雜訊，增加一共模抑制單元的二級設計，可將共模雜訊抑制範圍擴大到2.25吉赫至8吉赫。兩種共設計電路之訊號完整度及靜電放電防護能力，分別由眼圖量測及系統級靜電放電模擬得到驗證。 本文最後提出一設計方法，同時解決靜電放電防護陣列上的差模到共模轉換並提升信號完整度。建立該元件之等效電路模型後，內側及外側之間不對稱的等效電感及等效電阻，利用電感等化以及匹配電路來補償。模態轉換低於 -30 dB的範圍從4.1吉赫延伸至8.8吉赫。補償電路之眼高在每秒12千兆位元的傳輸速率下，有20%的改善。 | zh_TW |
| dc.description.abstract | In high-speed differential interfaces, electromagnetic interference, radio-frequency interference and electrostatic discharge protection are important issues. Radiated noise is excited when common-mode noise generated by practical system propagates through discontinuities such as connectors, cables, etc. The radiation may interfere external systems or internal wireless modules. Electrostatic discharges from external sources to input/output interfaces of electronic systems may cause fatal damage to internal devices and modules. To overcome these problems faced in high-speed interface, common-mode noise suppression and electrostatic discharge protection techniques have been developed for several decades. In the beginning of this dissertation, a design methodology is introduced to synthesize a reflective and an absorptive common-mode filter. Both designs implemented on integrated passive device process perform ultra-high differential-mode cutoff frequency and compact size of 768 × 724 μm2. The -10 dB common-mode noise suppression of reflective design is from 2.4 GHz to over 12.0 GHz. The absorptive design absorbs more than 80% of the common-mode noise from 3.0 GHz to 4.0 GHz, with 97.2% peak absorption at 3.5 GHz. Next, a co-design of electrostatic discharge protection device and common-mode filter implemented on printed circuit board is introduced since these components are essential in high-speed differential I/O interfaces. The common-mode equivalent circuit is pseudo-elliptic low-pass filter. The proposed one-stage design performs -10 dB common-mode noise suppression from 2.22 GHz to 2.76 GHz; the proposed two-stage design with additional common-mode suppression unit performs broadband suppression from 2.25 GHz to over 8 GHz. The signal integrity and the ESD protection function of proposed designs are investigated by eye diagram measurement and system-level ESD simulation. Finally, a design methodology is introduced to suppress the differential-mode to common-mode conversion and enhance signal integrity of electrostatic discharge protection array. The equivalent circuit model is extracted and the asymmetrical inductances and resistances between inner and outer lane are compensated by inductance equalization and LC matching circuit. The -30 dB mode conversion level is extended from 4.1 GHz to 8.8 GHz. The eye height of proposed compensation circuit is enhanced 20% at 12 Gb/s. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-11T14:51:50Z (GMT). No. of bitstreams: 1 U0001-0308202004031000.pdf: 11139819 bytes, checksum: 8bdb4890c4c7b7615a439d0920703ed7 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 國立台灣大學博士學位論文口試委員會審定書 # 誌謝 i 中文摘要 iii ABSTRACT v CONTENTS vii LIST OF FIGURES xi LIST OF TABLES xvi ACRONYMS xvii Chapter 1 Introduction 1 1.1 Research Motivation 1 1.2 Literature Survey 5 1.3 Contributions 10 Chapter 2 Circuit Theory and Background Knowledge 13 2.1 Network Analysis Techniques 14 2.1.1 Differenital Signaling and Fundamental Modes 14 2.1.2 Mixed-Mode S-Parameters 16 2.2 Microwave Filters with Lumped Elements 22 2.2.1 The Pole-Zero Concept 22 2.2.2 Butterworth Response 24 2.2.3 Chebyshev Response 28 2.2.4 Elliptic Response 32 2.3 Electrostatic Discharge 36 2.3.1 System Level ESD Tests 37 2.3.2 ESD Generator Modeling 39 2.3.3 ESD Protection Device 42 Chapter 3 Compact Common-Mode Filter with Bidirectional Noise Absorption in Integrated Passive Device Process 47 3.1 Proposed Design 48 3.1.1 Reflective Common-Mode Filter 48 3.1.2 Absorptive Common-Mode Filter 52 3.1.3 Design Procedure 56 3.2 Implementation of Proposed Design 57 3.3 Experimental Results 59 3.3.1 Frequency-Domain Response 59 3.3.2 Time-Domain Response 64 3.3.3 Discussion 68 3.4 Summary 69 Chapter 4 Co-design of Electrostatic Discharge Protection Device and Common Mode Suppression Circuit on Printed Circuit Board 71 4.1 Proposed Design 72 4.1.1 ESD Protection Device Modeling 74 4.1.2 Proposed One-stage Design 75 4.1.3 Proposed Two-stage Design 77 4.1.4 ESD Simulation 79 4.2 Implementation 81 4.3 Experimental Results 82 4.3.1 Frequency-Domain Response 82 4.3.2 Time-Domain Response 85 4.4 Summary 88 Chapter 5 Mode Conversion Suppression and Signal Integrity Enhancement for Electrostatic Discharge Protection Array 89 5.1 Mode Conversion on ESD Protection Array 90 5.1.1 S parameters 91 5.1.2 Antenna-Mode Current 94 5.2 Proposed Design and Methodology 96 5.2.1 Circuit Model of ESD Protection Array 96 5.2.2 Inductance Equalization 99 5.2.3 Resistance Equalization and Impedance Matching 100 5.2.4 Proposed Design 101 5.2.5 Mixed-Mode S Parameters Extraction of Asymmetrical Four-Port Network 103 5.2.6 Parameter Sweeping 104 5.2.7 Simulation Results 108 5.3 Experimental Results 111 5.3.1 Implementation and Fabrication 111 5.3.2 Frequency-Domain Response 111 5.3.3 Time-Domain Response 114 5.3.4 Discussion 116 5.4 Summary 117 Chapter 6 Conclusion 119 6.1 Conclusions of this Dissertation 119 6.2 Suggestions for Future Works 120 REFERENCE 122 PUBLICATION LIST 130 | |
| dc.language.iso | en | |
| dc.subject | 訊號完整度 | zh_TW |
| dc.subject | 吸收 | zh_TW |
| dc.subject | 共模雜訊 | zh_TW |
| dc.subject | 差動訊號傳輸 | zh_TW |
| dc.subject | 電磁干擾 | zh_TW |
| dc.subject | 靜電放電 | zh_TW |
| dc.subject | 高速差動介面 | zh_TW |
| dc.subject | 積體被動元件 | zh_TW |
| dc.subject | 模態轉換 | zh_TW |
| dc.subject | 射頻干擾 | zh_TW |
| dc.subject | 印刷電路板 | zh_TW |
| dc.subject | signal integrity (SI) | en |
| dc.subject | Absorption | en |
| dc.subject | common-mode noise | en |
| dc.subject | differential signaling | en |
| dc.subject | electromagnetic interference (EMI) | en |
| dc.subject | electrostatic discharge (ESD) | en |
| dc.subject | high-speed differential interface | en |
| dc.subject | integrated passive device (IPD) | en |
| dc.subject | mode conversion | en |
| dc.subject | radio-frequency interference (RFI) | en |
| dc.subject | printed circuit board (PCB) | en |
| dc.title | 靜電防護元件於高速差動介面中電磁暨射頻干擾抑制與訊號完整度改善 | zh_TW |
| dc.title | EMI/RFI Mitigation and SI Enhancement in High-Speed Differential Interfaces with ESD Protection Devices | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 邱政男(Cheng-Nan Chiu),陳士元(Shih-Yuan Chen),鄭宇翔(Yu-Hsiang Cheng),盧信嘉(Hsin-Chia Lu),鄭齊軒(Chi-Hsuan Cheng) | |
| dc.subject.keyword | 吸收,共模雜訊,差動訊號傳輸,電磁干擾,靜電放電,高速差動介面,積體被動元件,模態轉換,射頻干擾,印刷電路板,訊號完整度, | zh_TW |
| dc.subject.keyword | Absorption,common-mode noise,differential signaling,electromagnetic interference (EMI),electrostatic discharge (ESD),high-speed differential interface,integrated passive device (IPD),mode conversion,radio-frequency interference (RFI),printed circuit board (PCB),signal integrity (SI), | en |
| dc.relation.page | 131 | |
| dc.identifier.doi | 10.6342/NTU202002248 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2020-08-03 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2025-08-03 | - |
| 顯示於系所單位： | 電信工程學研究所 | |
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| U0001-0308202004031000.pdf 未授權公開取用 | 10.88 MB | Adobe PDF |
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